atombios_crtc.c 64.1 KB
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/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
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#include <drm/drm_fixed.h>
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#include "radeon.h"
#include "atom.h"
#include "atom-bits.h"

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static void atombios_overscan_setup(struct drm_crtc *crtc,
				    struct drm_display_mode *mode,
				    struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
	int a1, a2;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;

	switch (radeon_crtc->rmx_type) {
	case RMX_CENTER:
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		args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
		args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
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		break;
	case RMX_ASPECT:
		a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
		a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;

		if (a1 > a2) {
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			args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
			args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
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		} else if (a2 > a1) {
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			args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
			args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
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		}
		break;
	case RMX_FULL:
	default:
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		args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
		args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
		args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
		args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
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		break;
	}
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	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}

static void atombios_scaler_setup(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	ENABLE_SCALER_PS_ALLOCATION args;
	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
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	struct radeon_encoder *radeon_encoder =
		to_radeon_encoder(radeon_crtc->encoder);
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	/* fixme - fill in enc_priv for atom dac */
	enum radeon_tv_std tv_std = TV_STD_NTSC;
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	bool is_tv = false, is_cv = false;
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	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
		return;

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	if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
		struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
		tv_std = tv_dac->tv_std;
		is_tv = true;
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	}

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	memset(&args, 0, sizeof(args));

	args.ucScaler = radeon_crtc->crtc_id;

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	if (is_tv) {
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		switch (tv_std) {
		case TV_STD_NTSC:
		default:
			args.ucTVStandard = ATOM_TV_NTSC;
			break;
		case TV_STD_PAL:
			args.ucTVStandard = ATOM_TV_PAL;
			break;
		case TV_STD_PAL_M:
			args.ucTVStandard = ATOM_TV_PALM;
			break;
		case TV_STD_PAL_60:
			args.ucTVStandard = ATOM_TV_PAL60;
			break;
		case TV_STD_NTSC_J:
			args.ucTVStandard = ATOM_TV_NTSCJ;
			break;
		case TV_STD_SCART_PAL:
			args.ucTVStandard = ATOM_TV_PAL; /* ??? */
			break;
		case TV_STD_SECAM:
			args.ucTVStandard = ATOM_TV_SECAM;
			break;
		case TV_STD_PAL_CN:
			args.ucTVStandard = ATOM_TV_PALCN;
			break;
		}
		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
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	} else if (is_cv) {
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		args.ucTVStandard = ATOM_TV_CV;
		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
	} else {
		switch (radeon_crtc->rmx_type) {
		case RMX_FULL:
			args.ucEnable = ATOM_SCALER_EXPANSION;
			break;
		case RMX_CENTER:
			args.ucEnable = ATOM_SCALER_CENTER;
			break;
		case RMX_ASPECT:
			args.ucEnable = ATOM_SCALER_EXPANSION;
			break;
		default:
			if (ASIC_IS_AVIVO(rdev))
				args.ucEnable = ATOM_SCALER_DISABLE;
			else
				args.ucEnable = ATOM_SCALER_CENTER;
			break;
		}
	}
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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	if ((is_tv || is_cv)
	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
		atom_rv515_force_tv_scaler(rdev, radeon_crtc);
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	}
}

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static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index =
	    GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
	ENABLE_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucEnable = lock;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
	ENABLE_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucEnable = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
	ENABLE_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucEnable = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
	BLANK_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucBlanking = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

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static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
	ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;

	memset(&args, 0, sizeof(args));

	args.ucDispPipeId = radeon_crtc->crtc_id;
	args.ucEnable = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

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void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	switch (mode) {
	case DRM_MODE_DPMS_ON:
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		radeon_crtc->enabled = true;
		/* adjust pm to dpms changes BEFORE enabling crtcs */
		radeon_pm_compute_clocks(rdev);
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		atombios_enable_crtc(crtc, ATOM_ENABLE);
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		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
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			atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
		atombios_blank_crtc(crtc, ATOM_DISABLE);
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		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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		radeon_crtc_load_lut(crtc);
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		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
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		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
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		if (radeon_crtc->enabled)
			atombios_blank_crtc(crtc, ATOM_ENABLE);
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		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
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			atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
		atombios_enable_crtc(crtc, ATOM_DISABLE);
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		radeon_crtc->enabled = false;
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		/* adjust pm to dpms changes AFTER disabling crtcs */
		radeon_pm_compute_clocks(rdev);
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		break;
	}
}

static void
atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
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			     struct drm_display_mode *mode)
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{
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
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	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
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	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
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	u16 misc = 0;
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	memset(&args, 0, sizeof(args));
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	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
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	args.usH_Blanking_Time =
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		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
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	args.usV_Blanking_Time =
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		cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
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	args.usH_SyncOffset =
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		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
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	args.usH_SyncWidth =
		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
	args.usV_SyncOffset =
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		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
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	args.usV_SyncWidth =
		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
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	args.ucH_Border = radeon_crtc->h_border;
	args.ucV_Border = radeon_crtc->v_border;
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	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		misc |= ATOM_VSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		misc |= ATOM_HSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		misc |= ATOM_COMPOSITESYNC;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		misc |= ATOM_INTERLACE;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		misc |= ATOM_DOUBLE_CLOCK_MODE;

	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
	args.ucCRTC = radeon_crtc->crtc_id;
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	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}

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static void atombios_crtc_set_timing(struct drm_crtc *crtc,
				     struct drm_display_mode *mode)
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{
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
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	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
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	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
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	u16 misc = 0;
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	memset(&args, 0, sizeof(args));
	args.usH_Total = cpu_to_le16(mode->crtc_htotal);
	args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
	args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
	args.usH_SyncWidth =
		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
	args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
	args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
	args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
	args.usV_SyncWidth =
		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);

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	args.ucOverscanRight = radeon_crtc->h_border;
	args.ucOverscanLeft = radeon_crtc->h_border;
	args.ucOverscanBottom = radeon_crtc->v_border;
	args.ucOverscanTop = radeon_crtc->v_border;

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	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		misc |= ATOM_VSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		misc |= ATOM_HSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		misc |= ATOM_COMPOSITESYNC;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		misc |= ATOM_INTERLACE;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		misc |= ATOM_DOUBLE_CLOCK_MODE;

	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
	args.ucCRTC = radeon_crtc->crtc_id;
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	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}

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static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
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{
	u32 ss_cntl;

	if (ASIC_IS_DCE4(rdev)) {
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		switch (pll_id) {
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		case ATOM_PPLL1:
			ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
			WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
			break;
		case ATOM_PPLL2:
			ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
			WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
			break;
		case ATOM_DCPLL:
		case ATOM_PPLL_INVALID:
			return;
		}
	} else if (ASIC_IS_AVIVO(rdev)) {
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		switch (pll_id) {
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		case ATOM_PPLL1:
			ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
			ss_cntl &= ~1;
			WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
			break;
		case ATOM_PPLL2:
			ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
			ss_cntl &= ~1;
			WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
			break;
		case ATOM_DCPLL:
		case ATOM_PPLL_INVALID:
			return;
		}
	}
}


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union atom_enable_ss {
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	ENABLE_LVDS_SS_PARAMETERS lvds_ss;
	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
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	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
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	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
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	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
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};

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static void atombios_crtc_program_ss(struct radeon_device *rdev,
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				     int enable,
				     int pll_id,
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				     int crtc_id,
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				     struct radeon_atom_ss *ss)
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{
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	unsigned i;
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	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
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	union atom_enable_ss args;
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	if (!enable) {
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		for (i = 0; i < rdev->num_crtc; i++) {
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			if (rdev->mode_info.crtcs[i] &&
			    rdev->mode_info.crtcs[i]->enabled &&
			    i != crtc_id &&
			    pll_id == rdev->mode_info.crtcs[i]->pll_id) {
				/* one other crtc is using this pll don't turn
				 * off spread spectrum as it might turn off
				 * display on active crtc
				 */
				return;
			}
		}
	}

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	memset(&args, 0, sizeof(args));
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	if (ASIC_IS_DCE5(rdev)) {
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		args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
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		args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
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		switch (pll_id) {
		case ATOM_PPLL1:
			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
			break;
		case ATOM_PPLL2:
			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
			break;
		case ATOM_DCPLL:
			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
			break;
		case ATOM_PPLL_INVALID:
			return;
		}
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		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
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		args.v3.ucEnable = enable;
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		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
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			args.v3.ucEnable = ATOM_DISABLE;
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	} else if (ASIC_IS_DCE4(rdev)) {
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		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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		args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
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		switch (pll_id) {
		case ATOM_PPLL1:
			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
			break;
		case ATOM_PPLL2:
			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
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			break;
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		case ATOM_DCPLL:
			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
			break;
		case ATOM_PPLL_INVALID:
			return;
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		}
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		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
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		args.v2.ucEnable = enable;
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		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
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			args.v2.ucEnable = ATOM_DISABLE;
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	} else if (ASIC_IS_DCE3(rdev)) {
		args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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		args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
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		args.v1.ucSpreadSpectrumStep = ss->step;
		args.v1.ucSpreadSpectrumDelay = ss->delay;
		args.v1.ucSpreadSpectrumRange = ss->range;
		args.v1.ucPpll = pll_id;
		args.v1.ucEnable = enable;
	} else if (ASIC_IS_AVIVO(rdev)) {
494 495
		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
496
			atombios_disable_ss(rdev, pll_id);
497 498 499
			return;
		}
		args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
500
		args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
501 502 503 504
		args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
		args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
		args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
		args.lvds_ss_2.ucEnable = enable;
505
	} else {
506 507
		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
508
			atombios_disable_ss(rdev, pll_id);
509 510 511
			return;
		}
		args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
512
		args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
513 514 515
		args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
		args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
		args.lvds_ss.ucEnable = enable;
516
	}
517
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
518 519
}

520 521
union adjust_pixel_clock {
	ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
522
	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
523 524 525
};

static u32 atombios_adjust_pll(struct drm_crtc *crtc,
526
			       struct drm_display_mode *mode)
527
{
528
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
529 530
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
531 532 533
	struct drm_encoder *encoder = radeon_crtc->encoder;
	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
534
	u32 adjusted_clock = mode->clock;
535
	int encoder_mode = atombios_get_encoder_mode(encoder);
536
	u32 dp_clock = mode->clock;
537 538
	int bpc = radeon_get_monitor_bpc(connector);
	bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
539

540
	/* reset the pll flags */
541
	radeon_crtc->pll_flags = 0;
542 543

	if (ASIC_IS_AVIVO(rdev)) {
544 545 546
		if ((rdev->family == CHIP_RS600) ||
		    (rdev->family == CHIP_RS690) ||
		    (rdev->family == CHIP_RS740))
547 548
			radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
				RADEON_PLL_PREFER_CLOSEST_LOWER);
549 550

		if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)	/* range limits??? */
551
			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
552
		else
553
			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
554

555
		if (rdev->family < CHIP_RV770)
556
			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
557
		/* use frac fb div on APUs */
558
		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
559
			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 561 562
		/* use frac fb div on RS780/RS880 */
		if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
563 564
		if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
			radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
565
	} else {
566
		radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
567

568
		if (mode->clock > 200000)	/* range limits??? */
569
			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
570
		else
571
			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
572 573
	}

574 575 576 577 578 579
	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
	    (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
		if (connector) {
			struct radeon_connector *radeon_connector = to_radeon_connector(connector);
			struct radeon_connector_atom_dig *dig_connector =
				radeon_connector->con_priv;
580

581 582 583
			dp_clock = dig_connector->dp_clock;
		}
	}
584

585 586 587 588 589 590 591 592
	/* use recommended ref_div for ss */
	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
		if (radeon_crtc->ss_enabled) {
			if (radeon_crtc->ss.refdiv) {
				radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
				radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
				if (ASIC_IS_AVIVO(rdev))
					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
593 594 595 596
			}
		}
	}

597 598 599 600 601 602 603 604 605 606 607 608 609 610 611
	if (ASIC_IS_AVIVO(rdev)) {
		/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
			adjusted_clock = mode->clock * 2;
		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
			radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
			radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
	} else {
		if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
			radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
		if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
			radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
	}

612 613 614 615 616
	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
	 * accordingly based on the encoder/transmitter to work around
	 * special hw requirements.
	 */
	if (ASIC_IS_DCE3(rdev)) {
617 618 619
		union adjust_pixel_clock args;
		u8 frev, crev;
		int index;
620 621

		index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
622 623 624
		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
					   &crev))
			return adjusted_clock;
625 626 627 628 629 630 631 632 633 634

		memset(&args, 0, sizeof(args));

		switch (frev) {
		case 1:
			switch (crev) {
			case 1:
			case 2:
				args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
				args.v1.ucTransmitterID = radeon_encoder->encoder_id;
635
				args.v1.ucEncodeMode = encoder_mode;
636
				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
637 638
					args.v1.ucConfig |=
						ADJUST_DISPLAY_CONFIG_SS_ENABLE;
639 640 641 642 643

				atom_execute_table(rdev->mode_info.atom_context,
						   index, (uint32_t *)&args);
				adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
				break;
644 645 646 647 648
			case 3:
				args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
				args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
				args.v3.sInput.ucEncodeMode = encoder_mode;
				args.v3.sInput.ucDispPllConfig = 0;
649
				if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
650 651
					args.v3.sInput.ucDispPllConfig |=
						DISPPLL_CONFIG_SS_ENABLE;
652
				if (ENCODER_MODE_IS_DP(encoder_mode)) {
653 654 655 656 657
					args.v3.sInput.ucDispPllConfig |=
						DISPPLL_CONFIG_COHERENT_MODE;
					/* 16200 or 27000 */
					args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
				} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
658
					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
659 660 661 662 663
					if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
						/* deep color support */
						args.v3.sInput.usPixelClock =
							cpu_to_le16((mode->clock * bpc / 8) / 10);
					if (dig->coherent_mode)
664 665
						args.v3.sInput.ucDispPllConfig |=
							DISPPLL_CONFIG_COHERENT_MODE;
666
					if (is_duallink)
667
						args.v3.sInput.ucDispPllConfig |=
668
							DISPPLL_CONFIG_DUAL_LINK;
669
				}
670 671 672 673 674
				if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
				    ENCODER_OBJECT_ID_NONE)
					args.v3.sInput.ucExtTransmitterID =
						radeon_encoder_get_dp_bridge_encoder_id(encoder);
				else
675 676
					args.v3.sInput.ucExtTransmitterID = 0;

677 678 679 680
				atom_execute_table(rdev->mode_info.atom_context,
						   index, (uint32_t *)&args);
				adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
				if (args.v3.sOutput.ucRefDiv) {
681 682 683
					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
					radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
					radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
684 685
				}
				if (args.v3.sOutput.ucPostDiv) {
686 687 688
					radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
					radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
					radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
689 690
				}
				break;
691 692 693 694 695 696 697 698 699
			default:
				DRM_ERROR("Unknown table version %d %d\n", frev, crev);
				return adjusted_clock;
			}
			break;
		default:
			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
			return adjusted_clock;
		}
700
	}
701 702 703 704 705 706 707 708
	return adjusted_clock;
}

union set_pixel_clock {
	SET_PIXEL_CLOCK_PS_ALLOCATION base;
	PIXEL_CLOCK_PARAMETERS v1;
	PIXEL_CLOCK_PARAMETERS_V2 v2;
	PIXEL_CLOCK_PARAMETERS_V3 v3;
709
	PIXEL_CLOCK_PARAMETERS_V5 v5;
710
	PIXEL_CLOCK_PARAMETERS_V6 v6;
711 712
};

713 714 715
/* on DCE5, make sure the voltage is high enough to support the
 * required disp clk.
 */
716
static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
717
				    u32 dispclk)
718 719 720 721 722 723 724 725
{
	u8 frev, crev;
	int index;
	union set_pixel_clock args;

	memset(&args, 0, sizeof(args));

	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
726 727 728
	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
				   &crev))
		return;
729 730 731 732 733 734 735 736 737

	switch (frev) {
	case 1:
		switch (crev) {
		case 5:
			/* if the default dcpll clock is specified,
			 * SetPixelClock provides the dividers
			 */
			args.v5.ucCRTC = ATOM_CRTC_INVALID;
738
			args.v5.usPixelClock = cpu_to_le16(dispclk);
739 740
			args.v5.ucPpll = ATOM_DCPLL;
			break;
741 742 743 744
		case 6:
			/* if the default dcpll clock is specified,
			 * SetPixelClock provides the dividers
			 */
745
			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
746
			if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
747 748
				args.v6.ucPpll = ATOM_EXT_PLL1;
			else if (ASIC_IS_DCE6(rdev))
749 750 751
				args.v6.ucPpll = ATOM_PPLL0;
			else
				args.v6.ucPpll = ATOM_DCPLL;
752
			break;
753 754 755 756 757 758 759 760 761 762 763 764
		default:
			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
			return;
		}
		break;
	default:
		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		return;
	}
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

765
static void atombios_crtc_program_pll(struct drm_crtc *crtc,
766
				      u32 crtc_id,
767 768 769 770 771 772 773
				      int pll_id,
				      u32 encoder_mode,
				      u32 encoder_id,
				      u32 clock,
				      u32 ref_div,
				      u32 fb_div,
				      u32 frac_fb_div,
774
				      u32 post_div,
775 776 777
				      int bpc,
				      bool ss_enabled,
				      struct radeon_atom_ss *ss)
778 779 780 781
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	u8 frev, crev;
782
	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
783 784 785 786
	union set_pixel_clock args;

	memset(&args, 0, sizeof(args));

787 788 789
	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
				   &crev))
		return;
790 791 792 793 794

	switch (frev) {
	case 1:
		switch (crev) {
		case 1:
795 796 797
			if (clock == ATOM_DISABLE)
				return;
			args.v1.usPixelClock = cpu_to_le16(clock / 10);
798 799 800 801
			args.v1.usRefDiv = cpu_to_le16(ref_div);
			args.v1.usFbDiv = cpu_to_le16(fb_div);
			args.v1.ucFracFbDiv = frac_fb_div;
			args.v1.ucPostDiv = post_div;
802 803
			args.v1.ucPpll = pll_id;
			args.v1.ucCRTC = crtc_id;
804
			args.v1.ucRefDivSrc = 1;
805 806
			break;
		case 2:
807
			args.v2.usPixelClock = cpu_to_le16(clock / 10);
808 809 810 811
			args.v2.usRefDiv = cpu_to_le16(ref_div);
			args.v2.usFbDiv = cpu_to_le16(fb_div);
			args.v2.ucFracFbDiv = frac_fb_div;
			args.v2.ucPostDiv = post_div;
812 813
			args.v2.ucPpll = pll_id;
			args.v2.ucCRTC = crtc_id;
814
			args.v2.ucRefDivSrc = 1;
815 816
			break;
		case 3:
817
			args.v3.usPixelClock = cpu_to_le16(clock / 10);
818 819 820 821
			args.v3.usRefDiv = cpu_to_le16(ref_div);
			args.v3.usFbDiv = cpu_to_le16(fb_div);
			args.v3.ucFracFbDiv = frac_fb_div;
			args.v3.ucPostDiv = post_div;
822
			args.v3.ucPpll = pll_id;
823 824 825 826
			if (crtc_id == ATOM_CRTC2)
				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
			else
				args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
827 828
			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
				args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
829
			args.v3.ucTransmitterId = encoder_id;
830 831 832
			args.v3.ucEncoderMode = encoder_mode;
			break;
		case 5:
833 834
			args.v5.ucCRTC = crtc_id;
			args.v5.usPixelClock = cpu_to_le16(clock / 10);
835 836 837 838 839
			args.v5.ucRefDiv = ref_div;
			args.v5.usFbDiv = cpu_to_le16(fb_div);
			args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
			args.v5.ucPostDiv = post_div;
			args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
840 841
			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
842 843 844 845 846 847 848 849 850
			switch (bpc) {
			case 8:
			default:
				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
				break;
			case 10:
				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
				break;
			}
851
			args.v5.ucTransmitterID = encoder_id;
852
			args.v5.ucEncoderMode = encoder_mode;
853
			args.v5.ucPpll = pll_id;
854
			break;
855
		case 6:
856
			args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
857 858 859 860 861
			args.v6.ucRefDiv = ref_div;
			args.v6.usFbDiv = cpu_to_le16(fb_div);
			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
			args.v6.ucPostDiv = post_div;
			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
862 863
			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
864 865 866 867 868 869 870 871 872 873 874 875 876 877 878
			switch (bpc) {
			case 8:
			default:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
				break;
			case 10:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
				break;
			case 12:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
				break;
			case 16:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
				break;
			}
879 880 881 882
			args.v6.ucTransmitterID = encoder_id;
			args.v6.ucEncoderMode = encoder_mode;
			args.v6.ucPpll = pll_id;
			break;
883 884 885 886 887 888 889 890 891 892 893 894 895
		default:
			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
			return;
		}
		break;
	default:
		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		return;
	}

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

896
static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
897 898 899 900
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
901 902 903
	struct radeon_encoder *radeon_encoder =
		to_radeon_encoder(radeon_crtc->encoder);
	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
904 905 906

	radeon_crtc->bpc = 8;
	radeon_crtc->ss_enabled = false;
907

908
	if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
909
	    (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
910 911
		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		struct drm_connector *connector =
912
			radeon_get_connector_for_encoder(radeon_crtc->encoder);
913 914 915 916 917
		struct radeon_connector *radeon_connector =
			to_radeon_connector(connector);
		struct radeon_connector_atom_dig *dig_connector =
			radeon_connector->con_priv;
		int dp_clock;
918
		radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
919 920

		switch (encoder_mode) {
921
		case ATOM_ENCODER_MODE_DP_MST:
922 923 924
		case ATOM_ENCODER_MODE_DP:
			/* DP/eDP */
			dp_clock = dig_connector->dp_clock / 10;
925
			if (ASIC_IS_DCE4(rdev))
926 927
				radeon_crtc->ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
928 929 930 931
									 ASIC_INTERNAL_SS_ON_DP,
									 dp_clock);
			else {
				if (dp_clock == 16200) {
932 933 934
					radeon_crtc->ss_enabled =
						radeon_atombios_get_ppll_ss_info(rdev,
										 &radeon_crtc->ss,
935
										 ATOM_DP_SS_ID2);
936 937 938 939
					if (!radeon_crtc->ss_enabled)
						radeon_crtc->ss_enabled =
							radeon_atombios_get_ppll_ss_info(rdev,
											 &radeon_crtc->ss,
940
											 ATOM_DP_SS_ID1);
941
				} else
942 943 944
					radeon_crtc->ss_enabled =
						radeon_atombios_get_ppll_ss_info(rdev,
										 &radeon_crtc->ss,
945
										 ATOM_DP_SS_ID1);
946 947 948 949
			}
			break;
		case ATOM_ENCODER_MODE_LVDS:
			if (ASIC_IS_DCE4(rdev))
950 951 952 953 954
				radeon_crtc->ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev,
									 &radeon_crtc->ss,
									 dig->lcd_ss_id,
									 mode->clock / 10);
955
			else
956 957 958 959
				radeon_crtc->ss_enabled =
					radeon_atombios_get_ppll_ss_info(rdev,
									 &radeon_crtc->ss,
									 dig->lcd_ss_id);
960 961 962
			break;
		case ATOM_ENCODER_MODE_DVI:
			if (ASIC_IS_DCE4(rdev))
963 964 965
				radeon_crtc->ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev,
									 &radeon_crtc->ss,
966 967 968 969 970
									 ASIC_INTERNAL_SS_ON_TMDS,
									 mode->clock / 10);
			break;
		case ATOM_ENCODER_MODE_HDMI:
			if (ASIC_IS_DCE4(rdev))
971 972 973
				radeon_crtc->ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev,
									 &radeon_crtc->ss,
974 975 976 977 978 979 980 981
									 ASIC_INTERNAL_SS_ON_HDMI,
									 mode->clock / 10);
			break;
		default:
			break;
		}
	}

982
	/* adjust pixel clock as needed */
983 984 985 986 987 988 989 990 991 992
	radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);

	return true;
}

static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
993 994
	struct radeon_encoder *radeon_encoder =
		to_radeon_encoder(radeon_crtc->encoder);
995 996 997
	u32 pll_clock = mode->clock;
	u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
	struct radeon_pll *pll;
998
	int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017

	switch (radeon_crtc->pll_id) {
	case ATOM_PPLL1:
		pll = &rdev->clock.p1pll;
		break;
	case ATOM_PPLL2:
		pll = &rdev->clock.p2pll;
		break;
	case ATOM_DCPLL:
	case ATOM_PPLL_INVALID:
	default:
		pll = &rdev->clock.dcpll;
		break;
	}

	/* update pll params */
	pll->flags = radeon_crtc->pll_flags;
	pll->reference_div = radeon_crtc->pll_reference_div;
	pll->post_div = radeon_crtc->pll_post_div;
1018

1019 1020
	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		/* TV seems to prefer the legacy algo on some boards */
1021 1022
		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
					  &fb_div, &frac_fb_div, &ref_div, &post_div);
1023
	else if (ASIC_IS_AVIVO(rdev))
1024 1025
		radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
					 &fb_div, &frac_fb_div, &ref_div, &post_div);
1026
	else
1027 1028
		radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
					  &fb_div, &frac_fb_div, &ref_div, &post_div);
1029

1030 1031
	atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
				 radeon_crtc->crtc_id, &radeon_crtc->ss);
1032

1033 1034
	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
				  encoder_mode, radeon_encoder->encoder_id, mode->clock,
1035 1036
				  ref_div, fb_div, frac_fb_div, post_div,
				  radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1037

1038
	if (radeon_crtc->ss_enabled) {
1039 1040 1041
		/* calculate ss amount and step size */
		if (ASIC_IS_DCE4(rdev)) {
			u32 step_size;
1042 1043 1044
			u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;
			radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
			radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1045
				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1046 1047
			if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
				step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1048 1049
					(125 * 25 * pll->reference_freq / 100);
			else
1050
				step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1051
					(125 * 25 * pll->reference_freq / 100);
1052
			radeon_crtc->ss.step = step_size;
1053 1054
		}

1055 1056
		atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
					 radeon_crtc->crtc_id, &radeon_crtc->ss);
1057
	}
1058 1059
}

1060 1061 1062
static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 int x, int y, int atomic)
1063 1064 1065 1066 1067
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_framebuffer *radeon_fb;
1068
	struct drm_framebuffer *target_fb;
1069 1070 1071 1072
	struct drm_gem_object *obj;
	struct radeon_bo *rbo;
	uint64_t fb_location;
	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1073
	unsigned bankw, bankh, mtaspect, tile_split;
1074
	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1075
	u32 tmp, viewport_w, viewport_h;
1076 1077 1078
	int r;

	/* no fb bound */
1079
	if (!atomic && !crtc->fb) {
1080
		DRM_DEBUG_KMS("No FB bound\n");
1081 1082 1083
		return 0;
	}

1084 1085 1086 1087 1088 1089 1090 1091
	if (atomic) {
		radeon_fb = to_radeon_framebuffer(fb);
		target_fb = fb;
	}
	else {
		radeon_fb = to_radeon_framebuffer(crtc->fb);
		target_fb = crtc->fb;
	}
1092

1093 1094 1095
	/* If atomic, assume fb object is pinned & idle & fenced and
	 * just update base pointers
	 */
1096
	obj = radeon_fb->obj;
1097
	rbo = gem_to_radeon_bo(obj);
1098 1099 1100
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;
1101 1102 1103 1104 1105 1106 1107 1108 1109

	if (atomic)
		fb_location = radeon_bo_gpu_offset(rbo);
	else {
		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		if (unlikely(r != 0)) {
			radeon_bo_unreserve(rbo);
			return -EINVAL;
		}
1110
	}
1111

1112 1113 1114
	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
	radeon_bo_unreserve(rbo);

1115
	switch (target_fb->bits_per_pixel) {
1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
	case 8:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
		break;
	case 15:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
		break;
	case 16:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1127 1128 1129
#ifdef __BIG_ENDIAN
		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
#endif
1130 1131 1132 1133 1134
		break;
	case 24:
	case 32:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1135 1136 1137
#ifdef __BIG_ENDIAN
		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
#endif
1138 1139 1140
		break;
	default:
		DRM_ERROR("Unsupported screen depth %d\n",
1141
			  target_fb->bits_per_pixel);
1142 1143 1144
		return -EINVAL;
	}

1145
	if (tiling_flags & RADEON_TILING_MACRO) {
1146 1147 1148
		if (rdev->family >= CHIP_BONAIRE)
			tmp = rdev->config.cik.tile_config;
		else if (rdev->family >= CHIP_TAHITI)
1149 1150
			tmp = rdev->config.si.tile_config;
		else if (rdev->family >= CHIP_CAYMAN)
1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167
			tmp = rdev->config.cayman.tile_config;
		else
			tmp = rdev->config.evergreen.tile_config;

		switch ((tmp & 0xf0) >> 4) {
		case 0: /* 4 banks */
			fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
			break;
		case 1: /* 8 banks */
		default:
			fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
			break;
		case 2: /* 16 banks */
			fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
			break;
		}

1168
		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1169 1170 1171 1172 1173 1174

		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1175 1176 1177 1178
		if (rdev->family >= CHIP_BONAIRE) {
			/* XXX need to know more about the surface tiling mode */
			fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
		}
1179
	} else if (tiling_flags & RADEON_TILING_MICRO)
1180 1181
		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);

1182
	if (rdev->family >= CHIP_BONAIRE) {
1183 1184 1185 1186 1187 1188
		/* Read the pipe config from the 2D TILED SCANOUT mode.
		 * It should be the same for the other modes too, but not all
		 * modes set the pipe config field. */
		u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;

		fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1189 1190
	} else if ((rdev->family == CHIP_TAHITI) ||
		   (rdev->family == CHIP_PITCAIRN))
1191
		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1192 1193 1194
	else if ((rdev->family == CHIP_VERDE) ||
		 (rdev->family == CHIP_OLAND) ||
		 (rdev->family == CHIP_HAINAN)) /* for completeness.  HAINAN has no display hw */
1195 1196
		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);

1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228
	switch (radeon_crtc->crtc_id) {
	case 0:
		WREG32(AVIVO_D1VGA_CONTROL, 0);
		break;
	case 1:
		WREG32(AVIVO_D2VGA_CONTROL, 0);
		break;
	case 2:
		WREG32(EVERGREEN_D3VGA_CONTROL, 0);
		break;
	case 3:
		WREG32(EVERGREEN_D4VGA_CONTROL, 0);
		break;
	case 4:
		WREG32(EVERGREEN_D5VGA_CONTROL, 0);
		break;
	case 5:
		WREG32(EVERGREEN_D6VGA_CONTROL, 0);
		break;
	default:
		break;
	}

	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
	       upper_32_bits(fb_location));
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
	       upper_32_bits(fb_location));
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	       (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	       (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1229
	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1230 1231 1232 1233 1234

	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1235 1236
	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1237

1238
	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1239 1240 1241
	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

1242 1243 1244 1245 1246 1247
	if (rdev->family >= CHIP_BONAIRE)
		WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
		       target_fb->height);
	else
		WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
		       target_fb->height);
1248 1249 1250 1251
	x &= ~3;
	y &= ~1;
	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
	       (x << 16) | y);
1252 1253
	viewport_w = crtc->mode.hdisplay;
	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1254
	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1255
	       (viewport_w << 16) | viewport_h);
1256

1257 1258 1259 1260 1261 1262 1263 1264 1265
	/* pageflip setup */
	/* make sure flip is at vb rather than hb */
	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
	tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);

	/* set pageflip to happen anywhere in vblank interval */
	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

1266 1267
	if (!atomic && fb && fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(fb);
1268
		rbo = gem_to_radeon_bo(radeon_fb->obj);
1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
			return r;
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}

	/* Bytes per pixel may have changed */
	radeon_bandwidth_update(rdev);

	return 0;
}

1282 1283 1284
static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
				  struct drm_framebuffer *fb,
				  int x, int y, int atomic)
1285 1286 1287 1288 1289 1290
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_framebuffer *radeon_fb;
	struct drm_gem_object *obj;
1291
	struct radeon_bo *rbo;
1292
	struct drm_framebuffer *target_fb;
1293
	uint64_t fb_location;
1294
	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1295
	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1296
	u32 tmp, viewport_w, viewport_h;
1297
	int r;
1298

1299
	/* no fb bound */
1300
	if (!atomic && !crtc->fb) {
1301
		DRM_DEBUG_KMS("No FB bound\n");
1302 1303
		return 0;
	}
1304

1305 1306 1307 1308 1309 1310 1311 1312
	if (atomic) {
		radeon_fb = to_radeon_framebuffer(fb);
		target_fb = fb;
	}
	else {
		radeon_fb = to_radeon_framebuffer(crtc->fb);
		target_fb = crtc->fb;
	}
1313 1314

	obj = radeon_fb->obj;
1315
	rbo = gem_to_radeon_bo(obj);
1316 1317 1318
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;
1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330

	/* If atomic, assume fb object is pinned & idle & fenced and
	 * just update base pointers
	 */
	if (atomic)
		fb_location = radeon_bo_gpu_offset(rbo);
	else {
		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		if (unlikely(r != 0)) {
			radeon_bo_unreserve(rbo);
			return -EINVAL;
		}
1331
	}
1332 1333
	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
	radeon_bo_unreserve(rbo);
1334

1335
	switch (target_fb->bits_per_pixel) {
1336 1337 1338 1339 1340
	case 8:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
		    AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
		break;
1341 1342 1343 1344 1345 1346 1347 1348 1349
	case 15:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
		    AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
		break;
	case 16:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
		    AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1350 1351 1352
#ifdef __BIG_ENDIAN
		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
#endif
1353 1354 1355 1356 1357 1358
		break;
	case 24:
	case 32:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
		    AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1359 1360 1361
#ifdef __BIG_ENDIAN
		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
#endif
1362 1363 1364
		break;
	default:
		DRM_ERROR("Unsupported screen depth %d\n",
1365
			  target_fb->bits_per_pixel);
1366 1367 1368
		return -EINVAL;
	}

1369 1370 1371 1372 1373 1374 1375 1376
	if (rdev->family >= CHIP_R600) {
		if (tiling_flags & RADEON_TILING_MACRO)
			fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
		else if (tiling_flags & RADEON_TILING_MICRO)
			fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
	} else {
		if (tiling_flags & RADEON_TILING_MACRO)
			fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1377

1378 1379 1380
		if (tiling_flags & RADEON_TILING_MICRO)
			fb_format |= AVIVO_D1GRPH_TILED;
	}
1381

1382 1383 1384 1385
	if (radeon_crtc->crtc_id == 0)
		WREG32(AVIVO_D1VGA_CONTROL, 0);
	else
		WREG32(AVIVO_D2VGA_CONTROL, 0);
1386 1387 1388

	if (rdev->family >= CHIP_RV770) {
		if (radeon_crtc->crtc_id) {
1389 1390
			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
			WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1391
		} else {
1392 1393
			WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
			WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1394 1395
		}
	}
1396 1397 1398 1399 1400
	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	       (u32) fb_location);
	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
	       radeon_crtc->crtc_offset, (u32) fb_location);
	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1401 1402
	if (rdev->family >= CHIP_R600)
		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1403 1404 1405 1406 1407

	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1408 1409
	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1410

1411
	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1412 1413 1414 1415
	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1416
	       target_fb->height);
1417 1418 1419 1420
	x &= ~3;
	y &= ~1;
	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
	       (x << 16) | y);
1421 1422
	viewport_w = crtc->mode.hdisplay;
	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1423
	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1424
	       (viewport_w << 16) | viewport_h);
1425

1426 1427 1428 1429 1430 1431 1432 1433 1434
	/* pageflip setup */
	/* make sure flip is at vb rather than hb */
	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
	tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);

	/* set pageflip to happen anywhere in vblank interval */
	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

1435 1436
	if (!atomic && fb && fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(fb);
1437
		rbo = gem_to_radeon_bo(radeon_fb->obj);
1438 1439 1440 1441 1442
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
			return r;
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
1443
	}
1444 1445 1446 1447

	/* Bytes per pixel may have changed */
	radeon_bandwidth_update(rdev);

1448 1449 1450
	return 0;
}

1451 1452 1453 1454 1455 1456
int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
			   struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;

1457
	if (ASIC_IS_DCE4(rdev))
1458
		return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1459 1460 1461 1462 1463 1464 1465 1466
	else if (ASIC_IS_AVIVO(rdev))
		return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
	else
		return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
}

int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
                                  struct drm_framebuffer *fb,
1467
				  int x, int y, enum mode_set_atomic state)
1468 1469 1470 1471 1472
{
       struct drm_device *dev = crtc->dev;
       struct radeon_device *rdev = dev->dev_private;

	if (ASIC_IS_DCE4(rdev))
1473
		return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1474
	else if (ASIC_IS_AVIVO(rdev))
1475
		return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1476
	else
1477
		return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1478 1479
}

1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503
/* properly set additional regs when using atombios */
static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	u32 disp_merge_cntl;

	switch (radeon_crtc->crtc_id) {
	case 0:
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		break;
	case 1:
		disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
		WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
		WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
		WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
		break;
	}
}

1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
/**
 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
 *
 * @crtc: drm crtc
 *
 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
 */
static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct drm_crtc *test_crtc;
1515
	struct radeon_crtc *test_radeon_crtc;
1516 1517 1518 1519 1520 1521
	u32 pll_in_use = 0;

	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		if (crtc == test_crtc)
			continue;

1522 1523 1524
		test_radeon_crtc = to_radeon_crtc(test_crtc);
		if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
			pll_in_use |= (1 << test_radeon_crtc->pll_id);
1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540
	}
	return pll_in_use;
}

/**
 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
 *
 * @crtc: drm crtc
 *
 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
 * also in DP mode.  For DP, a single PPLL can be used for all DP
 * crtcs/encoders.
 */
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
1541
	struct drm_crtc *test_crtc;
1542
	struct radeon_crtc *test_radeon_crtc;
1543

1544 1545 1546 1547 1548 1549 1550 1551 1552
	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		if (crtc == test_crtc)
			continue;
		test_radeon_crtc = to_radeon_crtc(test_crtc);
		if (test_radeon_crtc->encoder &&
		    ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
			/* for DP use the same PLL for all */
			if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
				return test_radeon_crtc->pll_id;
1553 1554 1555 1556 1557
		}
	}
	return ATOM_PPLL_INVALID;
}

1558 1559 1560 1561 1562 1563 1564 1565 1566
/**
 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
 *
 * @crtc: drm crtc
 * @encoder: drm encoder
 *
 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
 * be shared (i.e., same clock).
 */
1567
static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1568
{
1569
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1570
	struct drm_device *dev = crtc->dev;
1571
	struct drm_crtc *test_crtc;
1572
	struct radeon_crtc *test_radeon_crtc;
1573
	u32 adjusted_clock, test_adjusted_clock;
1574

1575 1576 1577 1578
	adjusted_clock = radeon_crtc->adjusted_clock;

	if (adjusted_clock == 0)
		return ATOM_PPLL_INVALID;
1579

1580 1581 1582 1583 1584 1585 1586 1587 1588 1589
	list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
		if (crtc == test_crtc)
			continue;
		test_radeon_crtc = to_radeon_crtc(test_crtc);
		if (test_radeon_crtc->encoder &&
		    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
			/* check if we are already driving this connector with another crtc */
			if (test_radeon_crtc->connector == radeon_crtc->connector) {
				/* if we are, return that pll */
				if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1590
					return test_radeon_crtc->pll_id;
1591
			}
1592 1593 1594 1595 1596 1597 1598
			/* for non-DP check the clock */
			test_adjusted_clock = test_radeon_crtc->adjusted_clock;
			if ((crtc->mode.clock == test_crtc->mode.clock) &&
			    (adjusted_clock == test_adjusted_clock) &&
			    (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
			    (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
				return test_radeon_crtc->pll_id;
1599 1600 1601 1602 1603
		}
	}
	return ATOM_PPLL_INVALID;
}

1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618
/**
 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
 *
 * @crtc: drm crtc
 *
 * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
 * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
 * monitors a dedicated PPLL must be used.  If a particular board has
 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
 * as there is no need to program the PLL itself.  If we are not able to
 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
 * avoid messing up an existing monitor.
 *
 * Asic specific PLL information
 *
1619 1620 1621 1622 1623 1624
 * DCE 8.x
 * KB/KV
 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
 * CI
 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
 *
1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640
 * DCE 6.1
 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
 *
 * DCE 6.0
 * - PPLL0 is available to all UNIPHY (DP only)
 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
 *
 * DCE 5.0
 * - DCPLL is available to all UNIPHY (DP only)
 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
 *
 * DCE 3.0/4.0/4.1
 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
 *
 */
1641 1642
static int radeon_atom_pick_pll(struct drm_crtc *crtc)
{
1643
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1644 1645
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
1646 1647
	struct radeon_encoder *radeon_encoder =
		to_radeon_encoder(radeon_crtc->encoder);
1648 1649
	u32 pll_in_use;
	int pll;
1650

1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691
	if (ASIC_IS_DCE8(rdev)) {
		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
			if (rdev->clock.dp_extclk)
				/* skip PPLL programming if using ext clock */
				return ATOM_PPLL_INVALID;
			else {
				/* use the same PPLL for all DP monitors */
				pll = radeon_get_shared_dp_ppll(crtc);
				if (pll != ATOM_PPLL_INVALID)
					return pll;
			}
		} else {
			/* use the same PPLL for all monitors with the same clock */
			pll = radeon_get_shared_nondp_ppll(crtc);
			if (pll != ATOM_PPLL_INVALID)
				return pll;
		}
		/* otherwise, pick one of the plls */
		if ((rdev->family == CHIP_KAVERI) ||
		    (rdev->family == CHIP_KABINI)) {
			/* KB/KV has PPLL1 and PPLL2 */
			pll_in_use = radeon_get_pll_use_mask(crtc);
			if (!(pll_in_use & (1 << ATOM_PPLL2)))
				return ATOM_PPLL2;
			if (!(pll_in_use & (1 << ATOM_PPLL1)))
				return ATOM_PPLL1;
			DRM_ERROR("unable to allocate a PPLL\n");
			return ATOM_PPLL_INVALID;
		} else {
			/* CI has PPLL0, PPLL1, and PPLL2 */
			pll_in_use = radeon_get_pll_use_mask(crtc);
			if (!(pll_in_use & (1 << ATOM_PPLL2)))
				return ATOM_PPLL2;
			if (!(pll_in_use & (1 << ATOM_PPLL1)))
				return ATOM_PPLL1;
			if (!(pll_in_use & (1 << ATOM_PPLL0)))
				return ATOM_PPLL0;
			DRM_ERROR("unable to allocate a PPLL\n");
			return ATOM_PPLL_INVALID;
		}
	} else if (ASIC_IS_DCE61(rdev)) {
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708
		struct radeon_encoder_atom_dig *dig =
			radeon_encoder->enc_priv;

		if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
		    (dig->linkb == false))
			/* UNIPHY A uses PPLL2 */
			return ATOM_PPLL2;
		else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
			/* UNIPHY B/C/D/E/F */
			if (rdev->clock.dp_extclk)
				/* skip PPLL programming if using ext clock */
				return ATOM_PPLL_INVALID;
			else {
				/* use the same PPLL for all DP monitors */
				pll = radeon_get_shared_dp_ppll(crtc);
				if (pll != ATOM_PPLL_INVALID)
					return pll;
1709
			}
1710 1711 1712 1713 1714
		} else {
			/* use the same PPLL for all monitors with the same clock */
			pll = radeon_get_shared_nondp_ppll(crtc);
			if (pll != ATOM_PPLL_INVALID)
				return pll;
1715 1716
		}
		/* UNIPHY B/C/D/E/F */
1717 1718
		pll_in_use = radeon_get_pll_use_mask(crtc);
		if (!(pll_in_use & (1 << ATOM_PPLL0)))
1719
			return ATOM_PPLL0;
1720 1721 1722 1723
		if (!(pll_in_use & (1 << ATOM_PPLL1)))
			return ATOM_PPLL1;
		DRM_ERROR("unable to allocate a PPLL\n");
		return ATOM_PPLL_INVALID;
1724
	} else if (ASIC_IS_DCE4(rdev)) {
1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749
		/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
		 * depending on the asic:
		 * DCE4: PPLL or ext clock
		 * DCE5: PPLL, DCPLL, or ext clock
		 * DCE6: PPLL, PPLL0, or ext clock
		 *
		 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
		 * PPLL/DCPLL programming and only program the DP DTO for the
		 * crtc virtual pixel clock.
		 */
		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
			if (rdev->clock.dp_extclk)
				/* skip PPLL programming if using ext clock */
				return ATOM_PPLL_INVALID;
			else if (ASIC_IS_DCE6(rdev))
				/* use PPLL0 for all DP */
				return ATOM_PPLL0;
			else if (ASIC_IS_DCE5(rdev))
				/* use DCPLL for all DP */
				return ATOM_DCPLL;
			else {
				/* use the same PPLL for all DP monitors */
				pll = radeon_get_shared_dp_ppll(crtc);
				if (pll != ATOM_PPLL_INVALID)
					return pll;
1750
			}
1751
		} else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
1752 1753 1754 1755
			/* use the same PPLL for all monitors with the same clock */
			pll = radeon_get_shared_nondp_ppll(crtc);
			if (pll != ATOM_PPLL_INVALID)
				return pll;
1756
		}
1757 1758 1759
		/* all other cases */
		pll_in_use = radeon_get_pll_use_mask(crtc);
		if (!(pll_in_use & (1 << ATOM_PPLL1)))
1760
			return ATOM_PPLL1;
1761 1762
		if (!(pll_in_use & (1 << ATOM_PPLL2)))
			return ATOM_PPLL2;
1763 1764
		DRM_ERROR("unable to allocate a PPLL\n");
		return ATOM_PPLL_INVALID;
1765 1766
	} else {
		/* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780
		/* some atombios (observed in some DCE2/DCE3) code have a bug,
		 * the matching btw pll and crtc is done through
		 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
		 * pll (1 or 2) to select which register to write. ie if using
		 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
		 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
		 * choose which value to write. Which is reverse order from
		 * register logic. So only case that works is when pllid is
		 * same as crtcid or when both pll and crtc are enabled and
		 * both use same clock.
		 *
		 * So just return crtc id as if crtc and pll were hard linked
		 * together even if they aren't
		 */
1781
		return radeon_crtc->crtc_id;
1782
	}
1783 1784
}

1785
void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1786 1787
{
	/* always set DCPLL */
1788 1789 1790
	if (ASIC_IS_DCE6(rdev))
		atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
	else if (ASIC_IS_DCE4(rdev)) {
1791 1792 1793 1794 1795
		struct radeon_atom_ss ss;
		bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
								   ASIC_INTERNAL_SS_ON_DCPLL,
								   rdev->clock.default_dispclk);
		if (ss_enabled)
1796
			atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1797
		/* XXX: DCE5, make sure voltage, dispclk is high enough */
1798
		atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1799
		if (ss_enabled)
1800
			atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1801 1802 1803 1804
	}

}

1805 1806 1807 1808 1809 1810 1811 1812
int atombios_crtc_mode_set(struct drm_crtc *crtc,
			   struct drm_display_mode *mode,
			   struct drm_display_mode *adjusted_mode,
			   int x, int y, struct drm_framebuffer *old_fb)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
1813 1814
	struct radeon_encoder *radeon_encoder =
		to_radeon_encoder(radeon_crtc->encoder);
1815
	bool is_tvcv = false;
1816

1817 1818 1819
	if (radeon_encoder->active_device &
	    (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
		is_tvcv = true;
1820 1821 1822

	atombios_crtc_set_pll(crtc, adjusted_mode);

1823
	if (ASIC_IS_DCE4(rdev))
1824
		atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1825 1826 1827 1828 1829 1830
	else if (ASIC_IS_AVIVO(rdev)) {
		if (is_tvcv)
			atombios_crtc_set_timing(crtc, adjusted_mode);
		else
			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
	} else {
1831
		atombios_crtc_set_timing(crtc, adjusted_mode);
1832 1833
		if (radeon_crtc->crtc_id == 0)
			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1834
		radeon_legacy_atom_fixup(crtc);
1835
	}
1836
	atombios_crtc_set_base(crtc, x, y, old_fb);
1837 1838
	atombios_overscan_setup(crtc, mode, adjusted_mode);
	atombios_scaler_setup(crtc);
1839 1840 1841
	/* update the hw version fpr dpm */
	radeon_crtc->hw_mode = *adjusted_mode;

1842 1843 1844 1845
	return 0;
}

static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1846
				     const struct drm_display_mode *mode,
1847 1848
				     struct drm_display_mode *adjusted_mode)
{
1849 1850 1851 1852 1853 1854 1855 1856
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct drm_encoder *encoder;

	/* assign the encoder to the radeon crtc to avoid repeated lookups later */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			radeon_crtc->encoder = encoder;
1857
			radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1858 1859 1860
			break;
		}
	}
1861 1862 1863
	if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
		radeon_crtc->encoder = NULL;
		radeon_crtc->connector = NULL;
1864
		return false;
1865
	}
1866 1867
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		return false;
1868 1869
	if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
		return false;
1870 1871 1872 1873 1874 1875 1876
	/* pick pll */
	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
	/* if we can't get a PPLL for a non-DP encoder, fail */
	if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
	    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
		return false;

1877 1878 1879 1880 1881
	return true;
}

static void atombios_crtc_prepare(struct drm_crtc *crtc)
{
1882 1883
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
1884

1885 1886 1887 1888
	/* disable crtc pair power gating before programming */
	if (ASIC_IS_DCE6(rdev))
		atombios_powergate_crtc(crtc, ATOM_DISABLE);

1889
	atombios_lock_crtc(crtc, ATOM_ENABLE);
1890
	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1891 1892 1893 1894 1895
}

static void atombios_crtc_commit(struct drm_crtc *crtc)
{
	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1896
	atombios_lock_crtc(crtc, ATOM_DISABLE);
1897 1898
}

1899 1900 1901
static void atombios_crtc_disable(struct drm_crtc *crtc)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1902 1903
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
1904
	struct radeon_atom_ss ss;
1905
	int i;
1906

1907
	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922
	if (crtc->fb) {
		int r;
		struct radeon_framebuffer *radeon_fb;
		struct radeon_bo *rbo;

		radeon_fb = to_radeon_framebuffer(crtc->fb);
		rbo = gem_to_radeon_bo(radeon_fb->obj);
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r))
			DRM_ERROR("failed to reserve rbo before unpin\n");
		else {
			radeon_bo_unpin(rbo);
			radeon_bo_unreserve(rbo);
		}
	}
1923 1924 1925 1926 1927 1928
	/* disable the GRPH */
	if (ASIC_IS_DCE4(rdev))
		WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
	else if (ASIC_IS_AVIVO(rdev))
		WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

1929 1930
	if (ASIC_IS_DCE6(rdev))
		atombios_powergate_crtc(crtc, ATOM_ENABLE);
1931

1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943
	for (i = 0; i < rdev->num_crtc; i++) {
		if (rdev->mode_info.crtcs[i] &&
		    rdev->mode_info.crtcs[i]->enabled &&
		    i != radeon_crtc->crtc_id &&
		    radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
			/* one other crtc is using this pll don't turn
			 * off the pll
			 */
			goto done;
		}
	}

1944 1945 1946 1947 1948
	switch (radeon_crtc->pll_id) {
	case ATOM_PPLL1:
	case ATOM_PPLL2:
		/* disable the ppll */
		atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1949
					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1950
		break;
1951 1952
	case ATOM_PPLL0:
		/* disable the ppll */
1953 1954 1955
		if ((rdev->family == CHIP_ARUBA) ||
		    (rdev->family == CHIP_BONAIRE) ||
		    (rdev->family == CHIP_HAWAII))
1956 1957 1958
			atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
						  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
		break;
1959 1960 1961
	default:
		break;
	}
1962
done:
1963
	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1964
	radeon_crtc->adjusted_clock = 0;
1965
	radeon_crtc->encoder = NULL;
1966
	radeon_crtc->connector = NULL;
1967 1968
}

1969 1970 1971 1972 1973
static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
	.dpms = atombios_crtc_dpms,
	.mode_fixup = atombios_crtc_mode_fixup,
	.mode_set = atombios_crtc_mode_set,
	.mode_set_base = atombios_crtc_set_base,
1974
	.mode_set_base_atomic = atombios_crtc_set_base_atomic,
1975 1976
	.prepare = atombios_crtc_prepare,
	.commit = atombios_crtc_commit,
1977
	.load_lut = radeon_crtc_load_lut,
1978
	.disable = atombios_crtc_disable,
1979 1980 1981 1982 1983
};

void radeon_atombios_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc)
{
1984 1985 1986 1987 1988 1989
	struct radeon_device *rdev = dev->dev_private;

	if (ASIC_IS_DCE4(rdev)) {
		switch (radeon_crtc->crtc_id) {
		case 0:
		default:
1990
			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1991 1992
			break;
		case 1:
1993
			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1994 1995
			break;
		case 2:
1996
			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1997 1998
			break;
		case 3:
1999
			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2000 2001
			break;
		case 4:
2002
			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2003 2004
			break;
		case 5:
2005
			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2006 2007 2008 2009 2010 2011 2012 2013 2014
			break;
		}
	} else {
		if (radeon_crtc->crtc_id == 1)
			radeon_crtc->crtc_offset =
				AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
		else
			radeon_crtc->crtc_offset = 0;
	}
2015
	radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2016
	radeon_crtc->adjusted_clock = 0;
2017
	radeon_crtc->encoder = NULL;
2018
	radeon_crtc->connector = NULL;
2019 2020
	drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
}