atombios_crtc.c 50.7 KB
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/*
 * Copyright 2007-8 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 */
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
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#include <drm/drm_fixed.h>
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#include "radeon.h"
#include "atom.h"
#include "atom-bits.h"

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static void atombios_overscan_setup(struct drm_crtc *crtc,
				    struct drm_display_mode *mode,
				    struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	SET_CRTC_OVERSCAN_PS_ALLOCATION args;
	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
	int a1, a2;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;

	switch (radeon_crtc->rmx_type) {
	case RMX_CENTER:
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		args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
		args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
		args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
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		break;
	case RMX_ASPECT:
		a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
		a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;

		if (a1 > a2) {
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			args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
			args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
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		} else if (a2 > a1) {
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			args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
			args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
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		}
		break;
	case RMX_FULL:
	default:
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		args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
		args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
		args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
		args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
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		break;
	}
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	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}

static void atombios_scaler_setup(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	ENABLE_SCALER_PS_ALLOCATION args;
	int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
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	/* fixme - fill in enc_priv for atom dac */
	enum radeon_tv_std tv_std = TV_STD_NTSC;
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	bool is_tv = false, is_cv = false;
	struct drm_encoder *encoder;
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	if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
		return;

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	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		/* find tv std */
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
			if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
				struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
				tv_std = tv_dac->tv_std;
				is_tv = true;
			}
		}
	}

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	memset(&args, 0, sizeof(args));

	args.ucScaler = radeon_crtc->crtc_id;

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	if (is_tv) {
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		switch (tv_std) {
		case TV_STD_NTSC:
		default:
			args.ucTVStandard = ATOM_TV_NTSC;
			break;
		case TV_STD_PAL:
			args.ucTVStandard = ATOM_TV_PAL;
			break;
		case TV_STD_PAL_M:
			args.ucTVStandard = ATOM_TV_PALM;
			break;
		case TV_STD_PAL_60:
			args.ucTVStandard = ATOM_TV_PAL60;
			break;
		case TV_STD_NTSC_J:
			args.ucTVStandard = ATOM_TV_NTSCJ;
			break;
		case TV_STD_SCART_PAL:
			args.ucTVStandard = ATOM_TV_PAL; /* ??? */
			break;
		case TV_STD_SECAM:
			args.ucTVStandard = ATOM_TV_SECAM;
			break;
		case TV_STD_PAL_CN:
			args.ucTVStandard = ATOM_TV_PALCN;
			break;
		}
		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
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	} else if (is_cv) {
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		args.ucTVStandard = ATOM_TV_CV;
		args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
	} else {
		switch (radeon_crtc->rmx_type) {
		case RMX_FULL:
			args.ucEnable = ATOM_SCALER_EXPANSION;
			break;
		case RMX_CENTER:
			args.ucEnable = ATOM_SCALER_CENTER;
			break;
		case RMX_ASPECT:
			args.ucEnable = ATOM_SCALER_EXPANSION;
			break;
		default:
			if (ASIC_IS_AVIVO(rdev))
				args.ucEnable = ATOM_SCALER_DISABLE;
			else
				args.ucEnable = ATOM_SCALER_CENTER;
			break;
		}
	}
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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	if ((is_tv || is_cv)
	    && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
		atom_rv515_force_tv_scaler(rdev, radeon_crtc);
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	}
}

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static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index =
	    GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
	ENABLE_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucEnable = lock;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
	ENABLE_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucEnable = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
	ENABLE_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucEnable = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
	BLANK_CRTC_PS_ALLOCATION args;

	memset(&args, 0, sizeof(args));

	args.ucCRTC = radeon_crtc->crtc_id;
	args.ucBlanking = state;

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	switch (mode) {
	case DRM_MODE_DPMS_ON:
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		radeon_crtc->enabled = true;
		/* adjust pm to dpms changes BEFORE enabling crtcs */
		radeon_pm_compute_clocks(rdev);
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		atombios_enable_crtc(crtc, ATOM_ENABLE);
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		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
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			atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
		atombios_blank_crtc(crtc, ATOM_DISABLE);
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		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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		radeon_crtc_load_lut(crtc);
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		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
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		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
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		if (radeon_crtc->enabled)
			atombios_blank_crtc(crtc, ATOM_ENABLE);
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		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
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			atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
		atombios_enable_crtc(crtc, ATOM_DISABLE);
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		radeon_crtc->enabled = false;
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		/* adjust pm to dpms changes AFTER disabling crtcs */
		radeon_pm_compute_clocks(rdev);
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		break;
	}
}

static void
atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
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			     struct drm_display_mode *mode)
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{
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
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	SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
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	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
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	u16 misc = 0;
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	memset(&args, 0, sizeof(args));
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	args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
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	args.usH_Blanking_Time =
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		cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
	args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
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	args.usV_Blanking_Time =
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		cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
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	args.usH_SyncOffset =
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		cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
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	args.usH_SyncWidth =
		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
	args.usV_SyncOffset =
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		cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
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	args.usV_SyncWidth =
		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
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	args.ucH_Border = radeon_crtc->h_border;
	args.ucV_Border = radeon_crtc->v_border;
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	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		misc |= ATOM_VSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		misc |= ATOM_HSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		misc |= ATOM_COMPOSITESYNC;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		misc |= ATOM_INTERLACE;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		misc |= ATOM_DOUBLE_CLOCK_MODE;

	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
	args.ucCRTC = radeon_crtc->crtc_id;
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	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}

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static void atombios_crtc_set_timing(struct drm_crtc *crtc,
				     struct drm_display_mode *mode)
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{
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	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
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	SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
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	int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
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	u16 misc = 0;
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	memset(&args, 0, sizeof(args));
	args.usH_Total = cpu_to_le16(mode->crtc_htotal);
	args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
	args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
	args.usH_SyncWidth =
		cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
	args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
	args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
	args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
	args.usV_SyncWidth =
		cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);

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	args.ucOverscanRight = radeon_crtc->h_border;
	args.ucOverscanLeft = radeon_crtc->h_border;
	args.ucOverscanBottom = radeon_crtc->v_border;
	args.ucOverscanTop = radeon_crtc->v_border;

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	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		misc |= ATOM_VSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		misc |= ATOM_HSYNC_POLARITY;
	if (mode->flags & DRM_MODE_FLAG_CSYNC)
		misc |= ATOM_COMPOSITESYNC;
	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
		misc |= ATOM_INTERLACE;
	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		misc |= ATOM_DOUBLE_CLOCK_MODE;

	args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
	args.ucCRTC = radeon_crtc->crtc_id;
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	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}

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static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
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{
	u32 ss_cntl;

	if (ASIC_IS_DCE4(rdev)) {
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		switch (pll_id) {
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		case ATOM_PPLL1:
			ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
			WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
			break;
		case ATOM_PPLL2:
			ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
			WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
			break;
		case ATOM_DCPLL:
		case ATOM_PPLL_INVALID:
			return;
		}
	} else if (ASIC_IS_AVIVO(rdev)) {
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		switch (pll_id) {
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		case ATOM_PPLL1:
			ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
			ss_cntl &= ~1;
			WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
			break;
		case ATOM_PPLL2:
			ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
			ss_cntl &= ~1;
			WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
			break;
		case ATOM_DCPLL:
		case ATOM_PPLL_INVALID:
			return;
		}
	}
}


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union atom_enable_ss {
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	ENABLE_LVDS_SS_PARAMETERS lvds_ss;
	ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
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	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
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	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
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	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
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};

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static void atombios_crtc_program_ss(struct radeon_device *rdev,
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				     int enable,
				     int pll_id,
				     struct radeon_atom_ss *ss)
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{
	int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
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	union atom_enable_ss args;
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	memset(&args, 0, sizeof(args));
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	if (ASIC_IS_DCE5(rdev)) {
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		args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
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		args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
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		switch (pll_id) {
		case ATOM_PPLL1:
			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
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			args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
			args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
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			break;
		case ATOM_PPLL2:
			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
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			args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
			args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
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			break;
		case ATOM_DCPLL:
			args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
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			args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
			args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
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			break;
		case ATOM_PPLL_INVALID:
			return;
		}
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		args.v3.ucEnable = enable;
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		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
			args.v3.ucEnable = ATOM_DISABLE;
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	} else if (ASIC_IS_DCE4(rdev)) {
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		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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		args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
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		switch (pll_id) {
		case ATOM_PPLL1:
			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
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			args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
			args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
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			break;
		case ATOM_PPLL2:
			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
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			args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
			args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
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			break;
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		case ATOM_DCPLL:
			args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
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			args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
			args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
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			break;
		case ATOM_PPLL_INVALID:
			return;
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		}
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		args.v2.ucEnable = enable;
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		if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
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			args.v2.ucEnable = ATOM_DISABLE;
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	} else if (ASIC_IS_DCE3(rdev)) {
		args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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		args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
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		args.v1.ucSpreadSpectrumStep = ss->step;
		args.v1.ucSpreadSpectrumDelay = ss->delay;
		args.v1.ucSpreadSpectrumRange = ss->range;
		args.v1.ucPpll = pll_id;
		args.v1.ucEnable = enable;
	} else if (ASIC_IS_AVIVO(rdev)) {
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		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
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			atombios_disable_ss(rdev, pll_id);
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			return;
		}
		args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481
		args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
482 483 484 485
		args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
		args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
		args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
		args.lvds_ss_2.ucEnable = enable;
486
	} else {
487 488
		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
489
			atombios_disable_ss(rdev, pll_id);
490 491 492
			return;
		}
		args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
493
		args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
494 495 496
		args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
		args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
		args.lvds_ss.ucEnable = enable;
497
	}
498
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
499 500
}

501 502
union adjust_pixel_clock {
	ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
503
	ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
504 505 506 507
};

static u32 atombios_adjust_pll(struct drm_crtc *crtc,
			       struct drm_display_mode *mode,
508 509 510
			       struct radeon_pll *pll,
			       bool ss_enabled,
			       struct radeon_atom_ss *ss)
511 512 513 514 515
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct drm_encoder *encoder = NULL;
	struct radeon_encoder *radeon_encoder = NULL;
516
	struct drm_connector *connector = NULL;
517
	u32 adjusted_clock = mode->clock;
518
	int encoder_mode = 0;
519 520
	u32 dp_clock = mode->clock;
	int bpc = 8;
521
	bool is_duallink = false;
522

523 524
	/* reset the pll flags */
	pll->flags = 0;
525 526

	if (ASIC_IS_AVIVO(rdev)) {
527 528 529
		if ((rdev->family == CHIP_RS600) ||
		    (rdev->family == CHIP_RS690) ||
		    (rdev->family == CHIP_RS740))
530
			pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
531
				       RADEON_PLL_PREFER_CLOSEST_LOWER);
532 533 534 535 536

		if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)	/* range limits??? */
			pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
		else
			pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
537

538
		if (rdev->family < CHIP_RV770)
539
			pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
540
	} else {
541
		pll->flags |= RADEON_PLL_LEGACY;
542

543 544 545 546 547 548
		if (mode->clock > 200000)	/* range limits??? */
			pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
		else
			pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
	}

549 550
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
551
			radeon_encoder = to_radeon_encoder(encoder);
552
			connector = radeon_get_connector_for_encoder(encoder);
553
			if (connector && connector->display_info.bpc)
554
				bpc = connector->display_info.bpc;
555
			encoder_mode = atombios_get_encoder_mode(encoder);
556
			is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
A
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557
			if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
558
			    (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
559 560 561 562 563 564 565 566
				if (connector) {
					struct radeon_connector *radeon_connector = to_radeon_connector(connector);
					struct radeon_connector_atom_dig *dig_connector =
						radeon_connector->con_priv;

					dp_clock = dig_connector->dp_clock;
				}
			}
567

568 569 570 571 572 573
			/* use recommended ref_div for ss */
			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
				if (ss_enabled) {
					if (ss->refdiv) {
						pll->flags |= RADEON_PLL_USE_REF_DIV;
						pll->reference_div = ss->refdiv;
574 575
						if (ASIC_IS_AVIVO(rdev))
							pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
576 577 578
					}
				}
			}
579

580 581 582 583
			if (ASIC_IS_AVIVO(rdev)) {
				/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
					adjusted_clock = mode->clock * 2;
A
Alex Deucher 已提交
584
				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
585
					pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
586 587
				if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
					pll->flags |= RADEON_PLL_IS_LCD;
588 589
			} else {
				if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
590
					pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
591
				if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
592
					pll->flags |= RADEON_PLL_USE_REF_DIV;
593
			}
594
			break;
595 596 597
		}
	}

598 599 600 601 602
	/* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
	 * accordingly based on the encoder/transmitter to work around
	 * special hw requirements.
	 */
	if (ASIC_IS_DCE3(rdev)) {
603 604 605
		union adjust_pixel_clock args;
		u8 frev, crev;
		int index;
606 607

		index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
608 609 610
		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
					   &crev))
			return adjusted_clock;
611 612 613 614 615 616 617 618 619 620

		memset(&args, 0, sizeof(args));

		switch (frev) {
		case 1:
			switch (crev) {
			case 1:
			case 2:
				args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
				args.v1.ucTransmitterID = radeon_encoder->encoder_id;
621
				args.v1.ucEncodeMode = encoder_mode;
622
				if (ss_enabled && ss->percentage)
623 624
					args.v1.ucConfig |=
						ADJUST_DISPLAY_CONFIG_SS_ENABLE;
625 626 627 628 629

				atom_execute_table(rdev->mode_info.atom_context,
						   index, (uint32_t *)&args);
				adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
				break;
630 631 632 633 634
			case 3:
				args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
				args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
				args.v3.sInput.ucEncodeMode = encoder_mode;
				args.v3.sInput.ucDispPllConfig = 0;
635
				if (ss_enabled && ss->percentage)
636 637
					args.v3.sInput.ucDispPllConfig |=
						DISPPLL_CONFIG_SS_ENABLE;
638
				if (ENCODER_MODE_IS_DP(encoder_mode)) {
639 640 641 642 643
					args.v3.sInput.ucDispPllConfig |=
						DISPPLL_CONFIG_COHERENT_MODE;
					/* 16200 or 27000 */
					args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
				} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
644
					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
645 646 647 648 649
					if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
						/* deep color support */
						args.v3.sInput.usPixelClock =
							cpu_to_le16((mode->clock * bpc / 8) / 10);
					if (dig->coherent_mode)
650 651
						args.v3.sInput.ucDispPllConfig |=
							DISPPLL_CONFIG_COHERENT_MODE;
652
					if (is_duallink)
653
						args.v3.sInput.ucDispPllConfig |=
654
							DISPPLL_CONFIG_DUAL_LINK;
655
				}
656 657 658 659 660
				if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
				    ENCODER_OBJECT_ID_NONE)
					args.v3.sInput.ucExtTransmitterID =
						radeon_encoder_get_dp_bridge_encoder_id(encoder);
				else
661 662
					args.v3.sInput.ucExtTransmitterID = 0;

663 664 665 666
				atom_execute_table(rdev->mode_info.atom_context,
						   index, (uint32_t *)&args);
				adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
				if (args.v3.sOutput.ucRefDiv) {
667
					pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
668 669 670 671
					pll->flags |= RADEON_PLL_USE_REF_DIV;
					pll->reference_div = args.v3.sOutput.ucRefDiv;
				}
				if (args.v3.sOutput.ucPostDiv) {
672
					pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
673 674 675 676
					pll->flags |= RADEON_PLL_USE_POST_DIV;
					pll->post_div = args.v3.sOutput.ucPostDiv;
				}
				break;
677 678 679 680 681 682 683 684 685
			default:
				DRM_ERROR("Unknown table version %d %d\n", frev, crev);
				return adjusted_clock;
			}
			break;
		default:
			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
			return adjusted_clock;
		}
686
	}
687 688 689 690 691 692 693 694
	return adjusted_clock;
}

union set_pixel_clock {
	SET_PIXEL_CLOCK_PS_ALLOCATION base;
	PIXEL_CLOCK_PARAMETERS v1;
	PIXEL_CLOCK_PARAMETERS_V2 v2;
	PIXEL_CLOCK_PARAMETERS_V3 v3;
695
	PIXEL_CLOCK_PARAMETERS_V5 v5;
696
	PIXEL_CLOCK_PARAMETERS_V6 v6;
697 698
};

699 700 701
/* on DCE5, make sure the voltage is high enough to support the
 * required disp clk.
 */
702
static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
703
				    u32 dispclk)
704 705 706 707 708 709 710 711
{
	u8 frev, crev;
	int index;
	union set_pixel_clock args;

	memset(&args, 0, sizeof(args));

	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
712 713 714
	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
				   &crev))
		return;
715 716 717 718 719 720 721 722 723

	switch (frev) {
	case 1:
		switch (crev) {
		case 5:
			/* if the default dcpll clock is specified,
			 * SetPixelClock provides the dividers
			 */
			args.v5.ucCRTC = ATOM_CRTC_INVALID;
724
			args.v5.usPixelClock = cpu_to_le16(dispclk);
725 726
			args.v5.ucPpll = ATOM_DCPLL;
			break;
727 728 729 730
		case 6:
			/* if the default dcpll clock is specified,
			 * SetPixelClock provides the dividers
			 */
731
			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
732 733
			args.v6.ucPpll = ATOM_DCPLL;
			break;
734 735 736 737 738 739 740 741 742 743 744 745
		default:
			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
			return;
		}
		break;
	default:
		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		return;
	}
	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

746
static void atombios_crtc_program_pll(struct drm_crtc *crtc,
747
				      u32 crtc_id,
748 749 750 751 752 753 754
				      int pll_id,
				      u32 encoder_mode,
				      u32 encoder_id,
				      u32 clock,
				      u32 ref_div,
				      u32 fb_div,
				      u32 frac_fb_div,
755
				      u32 post_div,
756 757 758
				      int bpc,
				      bool ss_enabled,
				      struct radeon_atom_ss *ss)
759 760 761 762
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	u8 frev, crev;
763
	int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
764 765 766 767
	union set_pixel_clock args;

	memset(&args, 0, sizeof(args));

768 769 770
	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
				   &crev))
		return;
771 772 773 774 775

	switch (frev) {
	case 1:
		switch (crev) {
		case 1:
776 777 778
			if (clock == ATOM_DISABLE)
				return;
			args.v1.usPixelClock = cpu_to_le16(clock / 10);
779 780 781 782
			args.v1.usRefDiv = cpu_to_le16(ref_div);
			args.v1.usFbDiv = cpu_to_le16(fb_div);
			args.v1.ucFracFbDiv = frac_fb_div;
			args.v1.ucPostDiv = post_div;
783 784
			args.v1.ucPpll = pll_id;
			args.v1.ucCRTC = crtc_id;
785
			args.v1.ucRefDivSrc = 1;
786 787
			break;
		case 2:
788
			args.v2.usPixelClock = cpu_to_le16(clock / 10);
789 790 791 792
			args.v2.usRefDiv = cpu_to_le16(ref_div);
			args.v2.usFbDiv = cpu_to_le16(fb_div);
			args.v2.ucFracFbDiv = frac_fb_div;
			args.v2.ucPostDiv = post_div;
793 794
			args.v2.ucPpll = pll_id;
			args.v2.ucCRTC = crtc_id;
795
			args.v2.ucRefDivSrc = 1;
796 797
			break;
		case 3:
798
			args.v3.usPixelClock = cpu_to_le16(clock / 10);
799 800 801 802
			args.v3.usRefDiv = cpu_to_le16(ref_div);
			args.v3.usFbDiv = cpu_to_le16(fb_div);
			args.v3.ucFracFbDiv = frac_fb_div;
			args.v3.ucPostDiv = post_div;
803 804
			args.v3.ucPpll = pll_id;
			args.v3.ucMiscInfo = (pll_id << 2);
805 806
			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
				args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
807
			args.v3.ucTransmitterId = encoder_id;
808 809 810
			args.v3.ucEncoderMode = encoder_mode;
			break;
		case 5:
811 812
			args.v5.ucCRTC = crtc_id;
			args.v5.usPixelClock = cpu_to_le16(clock / 10);
813 814 815 816 817
			args.v5.ucRefDiv = ref_div;
			args.v5.usFbDiv = cpu_to_le16(fb_div);
			args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
			args.v5.ucPostDiv = post_div;
			args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
818 819
			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
820 821 822 823 824 825 826 827 828
			switch (bpc) {
			case 8:
			default:
				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
				break;
			case 10:
				args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
				break;
			}
829
			args.v5.ucTransmitterID = encoder_id;
830
			args.v5.ucEncoderMode = encoder_mode;
831
			args.v5.ucPpll = pll_id;
832
			break;
833
		case 6:
834
			args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
835 836 837 838 839
			args.v6.ucRefDiv = ref_div;
			args.v6.usFbDiv = cpu_to_le16(fb_div);
			args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
			args.v6.ucPostDiv = post_div;
			args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
840 841
			if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
842 843 844 845 846 847 848 849 850 851 852 853 854 855 856
			switch (bpc) {
			case 8:
			default:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
				break;
			case 10:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
				break;
			case 12:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
				break;
			case 16:
				args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
				break;
			}
857 858 859 860
			args.v6.ucTransmitterID = encoder_id;
			args.v6.ucEncoderMode = encoder_mode;
			args.v6.ucPpll = pll_id;
			break;
861 862 863 864 865 866 867 868 869 870 871 872 873
		default:
			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
			return;
		}
		break;
	default:
		DRM_ERROR("Unknown table version %d %d\n", frev, crev);
		return;
	}

	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}

874 875 876 877 878 879 880 881 882 883 884 885
static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct drm_encoder *encoder = NULL;
	struct radeon_encoder *radeon_encoder = NULL;
	u32 pll_clock = mode->clock;
	u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
	struct radeon_pll *pll;
	u32 adjusted_clock;
	int encoder_mode = 0;
886 887
	struct radeon_atom_ss ss;
	bool ss_enabled = false;
888
	int bpc = 8;
889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		if (encoder->crtc == crtc) {
			radeon_encoder = to_radeon_encoder(encoder);
			encoder_mode = atombios_get_encoder_mode(encoder);
			break;
		}
	}

	if (!radeon_encoder)
		return;

	switch (radeon_crtc->pll_id) {
	case ATOM_PPLL1:
		pll = &rdev->clock.p1pll;
		break;
	case ATOM_PPLL2:
		pll = &rdev->clock.p2pll;
		break;
	case ATOM_DCPLL:
	case ATOM_PPLL_INVALID:
	default:
		pll = &rdev->clock.dcpll;
		break;
	}

915 916 917 918 919 920 921 922 923 924
	if (radeon_encoder->active_device &
	    (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
		struct drm_connector *connector =
			radeon_get_connector_for_encoder(encoder);
		struct radeon_connector *radeon_connector =
			to_radeon_connector(connector);
		struct radeon_connector_atom_dig *dig_connector =
			radeon_connector->con_priv;
		int dp_clock;
925
		bpc = connector->display_info.bpc;
926 927

		switch (encoder_mode) {
928
		case ATOM_ENCODER_MODE_DP_MST:
929 930 931
		case ATOM_ENCODER_MODE_DP:
			/* DP/eDP */
			dp_clock = dig_connector->dp_clock / 10;
932 933 934 935 936 937 938
			if (ASIC_IS_DCE4(rdev))
				ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev, &ss,
									 ASIC_INTERNAL_SS_ON_DP,
									 dp_clock);
			else {
				if (dp_clock == 16200) {
939
					ss_enabled =
940 941
						radeon_atombios_get_ppll_ss_info(rdev, &ss,
										 ATOM_DP_SS_ID2);
942 943
					if (!ss_enabled)
						ss_enabled =
944 945
							radeon_atombios_get_ppll_ss_info(rdev, &ss,
											 ATOM_DP_SS_ID1);
946
				} else
947 948
					ss_enabled =
						radeon_atombios_get_ppll_ss_info(rdev, &ss,
949
										 ATOM_DP_SS_ID1);
950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979
			}
			break;
		case ATOM_ENCODER_MODE_LVDS:
			if (ASIC_IS_DCE4(rdev))
				ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
									      dig->lcd_ss_id,
									      mode->clock / 10);
			else
				ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
									      dig->lcd_ss_id);
			break;
		case ATOM_ENCODER_MODE_DVI:
			if (ASIC_IS_DCE4(rdev))
				ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev, &ss,
									 ASIC_INTERNAL_SS_ON_TMDS,
									 mode->clock / 10);
			break;
		case ATOM_ENCODER_MODE_HDMI:
			if (ASIC_IS_DCE4(rdev))
				ss_enabled =
					radeon_atombios_get_asic_ss_info(rdev, &ss,
									 ASIC_INTERNAL_SS_ON_HDMI,
									 mode->clock / 10);
			break;
		default:
			break;
		}
	}

980
	/* adjust pixel clock as needed */
981
	adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
982

983 984 985 986 987
	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
		/* TV seems to prefer the legacy algo on some boards */
		radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
					  &ref_div, &post_div);
	else if (ASIC_IS_AVIVO(rdev))
988 989 990 991 992
		radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
					 &ref_div, &post_div);
	else
		radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
					  &ref_div, &post_div);
993

994
	atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
995

996 997
	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
				  encoder_mode, radeon_encoder->encoder_id, mode->clock,
998
				  ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
999

1000 1001 1002 1003 1004 1005
	if (ss_enabled) {
		/* calculate ss amount and step size */
		if (ASIC_IS_DCE4(rdev)) {
			u32 step_size;
			u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
			ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1006
			ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1007 1008 1009 1010 1011 1012 1013 1014 1015 1016
				ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
			if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
				step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
					(125 * 25 * pll->reference_freq / 100);
			else
				step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
					(125 * 25 * pll->reference_freq / 100);
			ss.step = step_size;
		}

1017
		atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1018
	}
1019 1020
}

1021 1022 1023
static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
				 struct drm_framebuffer *fb,
				 int x, int y, int atomic)
1024 1025 1026 1027 1028
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_framebuffer *radeon_fb;
1029
	struct drm_framebuffer *target_fb;
1030 1031 1032 1033
	struct drm_gem_object *obj;
	struct radeon_bo *rbo;
	uint64_t fb_location;
	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1034
	unsigned bankw, bankh, mtaspect, tile_split;
1035
	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1036
	u32 tmp, viewport_w, viewport_h;
1037 1038 1039
	int r;

	/* no fb bound */
1040
	if (!atomic && !crtc->fb) {
1041
		DRM_DEBUG_KMS("No FB bound\n");
1042 1043 1044
		return 0;
	}

1045 1046 1047 1048 1049 1050 1051 1052
	if (atomic) {
		radeon_fb = to_radeon_framebuffer(fb);
		target_fb = fb;
	}
	else {
		radeon_fb = to_radeon_framebuffer(crtc->fb);
		target_fb = crtc->fb;
	}
1053

1054 1055 1056
	/* If atomic, assume fb object is pinned & idle & fenced and
	 * just update base pointers
	 */
1057
	obj = radeon_fb->obj;
1058
	rbo = gem_to_radeon_bo(obj);
1059 1060 1061
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;
1062 1063 1064 1065 1066 1067 1068 1069 1070

	if (atomic)
		fb_location = radeon_bo_gpu_offset(rbo);
	else {
		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		if (unlikely(r != 0)) {
			radeon_bo_unreserve(rbo);
			return -EINVAL;
		}
1071
	}
1072

1073 1074 1075
	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
	radeon_bo_unreserve(rbo);

1076
	switch (target_fb->bits_per_pixel) {
1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	case 8:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
		break;
	case 15:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
		break;
	case 16:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1088 1089 1090
#ifdef __BIG_ENDIAN
		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
#endif
1091 1092 1093 1094 1095
		break;
	case 24:
	case 32:
		fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
			     EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1096 1097 1098
#ifdef __BIG_ENDIAN
		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
#endif
1099 1100 1101
		break;
	default:
		DRM_ERROR("Unsupported screen depth %d\n",
1102
			  target_fb->bits_per_pixel);
1103 1104 1105
		return -EINVAL;
	}

1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124
	if (tiling_flags & RADEON_TILING_MACRO) {
		if (rdev->family >= CHIP_CAYMAN)
			tmp = rdev->config.cayman.tile_config;
		else
			tmp = rdev->config.evergreen.tile_config;

		switch ((tmp & 0xf0) >> 4) {
		case 0: /* 4 banks */
			fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
			break;
		case 1: /* 8 banks */
		default:
			fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
			break;
		case 2: /* 16 banks */
			fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
			break;
		}

1125
		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1126 1127 1128 1129 1130 1131

		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
		fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1132
	} else if (tiling_flags & RADEON_TILING_MICRO)
1133 1134
		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);

1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166
	switch (radeon_crtc->crtc_id) {
	case 0:
		WREG32(AVIVO_D1VGA_CONTROL, 0);
		break;
	case 1:
		WREG32(AVIVO_D2VGA_CONTROL, 0);
		break;
	case 2:
		WREG32(EVERGREEN_D3VGA_CONTROL, 0);
		break;
	case 3:
		WREG32(EVERGREEN_D4VGA_CONTROL, 0);
		break;
	case 4:
		WREG32(EVERGREEN_D5VGA_CONTROL, 0);
		break;
	case 5:
		WREG32(EVERGREEN_D6VGA_CONTROL, 0);
		break;
	default:
		break;
	}

	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
	       upper_32_bits(fb_location));
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
	       upper_32_bits(fb_location));
	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	       (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	       (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
	WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1167
	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1168 1169 1170 1171 1172

	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
	WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
	WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
	WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1173 1174
	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1175

1176
	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1177 1178 1179 1180
	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

	WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1181
	       target_fb->height);
1182 1183 1184 1185
	x &= ~3;
	y &= ~1;
	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
	       (x << 16) | y);
1186 1187
	viewport_w = crtc->mode.hdisplay;
	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1188
	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1189
	       (viewport_w << 16) | viewport_h);
1190

1191 1192 1193 1194 1195 1196 1197 1198 1199
	/* pageflip setup */
	/* make sure flip is at vb rather than hb */
	tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
	tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);

	/* set pageflip to happen anywhere in vblank interval */
	WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

1200 1201
	if (!atomic && fb && fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(fb);
1202
		rbo = gem_to_radeon_bo(radeon_fb->obj);
1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
			return r;
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}

	/* Bytes per pixel may have changed */
	radeon_bandwidth_update(rdev);

	return 0;
}

1216 1217 1218
static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
				  struct drm_framebuffer *fb,
				  int x, int y, int atomic)
1219 1220 1221 1222 1223 1224
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_framebuffer *radeon_fb;
	struct drm_gem_object *obj;
1225
	struct radeon_bo *rbo;
1226
	struct drm_framebuffer *target_fb;
1227
	uint64_t fb_location;
1228
	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1229
	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1230
	u32 tmp, viewport_w, viewport_h;
1231
	int r;
1232

1233
	/* no fb bound */
1234
	if (!atomic && !crtc->fb) {
1235
		DRM_DEBUG_KMS("No FB bound\n");
1236 1237
		return 0;
	}
1238

1239 1240 1241 1242 1243 1244 1245 1246
	if (atomic) {
		radeon_fb = to_radeon_framebuffer(fb);
		target_fb = fb;
	}
	else {
		radeon_fb = to_radeon_framebuffer(crtc->fb);
		target_fb = crtc->fb;
	}
1247 1248

	obj = radeon_fb->obj;
1249
	rbo = gem_to_radeon_bo(obj);
1250 1251 1252
	r = radeon_bo_reserve(rbo, false);
	if (unlikely(r != 0))
		return r;
1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264

	/* If atomic, assume fb object is pinned & idle & fenced and
	 * just update base pointers
	 */
	if (atomic)
		fb_location = radeon_bo_gpu_offset(rbo);
	else {
		r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
		if (unlikely(r != 0)) {
			radeon_bo_unreserve(rbo);
			return -EINVAL;
		}
1265
	}
1266 1267
	radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
	radeon_bo_unreserve(rbo);
1268

1269
	switch (target_fb->bits_per_pixel) {
1270 1271 1272 1273 1274
	case 8:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
		    AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
		break;
1275 1276 1277 1278 1279 1280 1281 1282 1283
	case 15:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
		    AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
		break;
	case 16:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
		    AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1284 1285 1286
#ifdef __BIG_ENDIAN
		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
#endif
1287 1288 1289 1290 1291 1292
		break;
	case 24:
	case 32:
		fb_format =
		    AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
		    AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1293 1294 1295
#ifdef __BIG_ENDIAN
		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
#endif
1296 1297 1298
		break;
	default:
		DRM_ERROR("Unsupported screen depth %d\n",
1299
			  target_fb->bits_per_pixel);
1300 1301 1302
		return -EINVAL;
	}

1303 1304 1305 1306 1307 1308 1309 1310
	if (rdev->family >= CHIP_R600) {
		if (tiling_flags & RADEON_TILING_MACRO)
			fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
		else if (tiling_flags & RADEON_TILING_MICRO)
			fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
	} else {
		if (tiling_flags & RADEON_TILING_MACRO)
			fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1311

1312 1313 1314
		if (tiling_flags & RADEON_TILING_MICRO)
			fb_format |= AVIVO_D1GRPH_TILED;
	}
1315

1316 1317 1318 1319
	if (radeon_crtc->crtc_id == 0)
		WREG32(AVIVO_D1VGA_CONTROL, 0);
	else
		WREG32(AVIVO_D2VGA_CONTROL, 0);
1320 1321 1322

	if (rdev->family >= CHIP_RV770) {
		if (radeon_crtc->crtc_id) {
1323 1324
			WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
			WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1325
		} else {
1326 1327
			WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
			WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1328 1329
		}
	}
1330 1331 1332 1333 1334
	WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
	       (u32) fb_location);
	WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
	       radeon_crtc->crtc_offset, (u32) fb_location);
	WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1335 1336
	if (rdev->family >= CHIP_R600)
		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1337 1338 1339 1340 1341

	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
	WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
	WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
	WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1342 1343
	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1344

1345
	fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1346 1347 1348 1349
	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

	WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1350
	       target_fb->height);
1351 1352 1353 1354
	x &= ~3;
	y &= ~1;
	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
	       (x << 16) | y);
1355 1356
	viewport_w = crtc->mode.hdisplay;
	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1357
	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1358
	       (viewport_w << 16) | viewport_h);
1359

1360 1361 1362 1363 1364 1365 1366 1367 1368
	/* pageflip setup */
	/* make sure flip is at vb rather than hb */
	tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
	tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
	WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);

	/* set pageflip to happen anywhere in vblank interval */
	WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

1369 1370
	if (!atomic && fb && fb != crtc->fb) {
		radeon_fb = to_radeon_framebuffer(fb);
1371
		rbo = gem_to_radeon_bo(radeon_fb->obj);
1372 1373 1374 1375 1376
		r = radeon_bo_reserve(rbo, false);
		if (unlikely(r != 0))
			return r;
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
1377
	}
1378 1379 1380 1381

	/* Bytes per pixel may have changed */
	radeon_bandwidth_update(rdev);

1382 1383 1384
	return 0;
}

1385 1386 1387 1388 1389 1390
int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
			   struct drm_framebuffer *old_fb)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;

1391
	if (ASIC_IS_DCE4(rdev))
1392
		return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1393 1394 1395 1396 1397 1398 1399 1400
	else if (ASIC_IS_AVIVO(rdev))
		return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
	else
		return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
}

int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
                                  struct drm_framebuffer *fb,
1401
				  int x, int y, enum mode_set_atomic state)
1402 1403 1404 1405 1406
{
       struct drm_device *dev = crtc->dev;
       struct radeon_device *rdev = dev->dev_private;

	if (ASIC_IS_DCE4(rdev))
1407
		return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1408
	else if (ASIC_IS_AVIVO(rdev))
1409
		return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1410
	else
1411
		return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1412 1413
}

1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437
/* properly set additional regs when using atombios */
static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
{
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	u32 disp_merge_cntl;

	switch (radeon_crtc->crtc_id) {
	case 0:
		disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
		WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
		break;
	case 1:
		disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
		disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
		WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
		WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
		WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
		break;
	}
}

1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449
static int radeon_atom_pick_pll(struct drm_crtc *crtc)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
	struct drm_encoder *test_encoder;
	struct drm_crtc *test_crtc;
	uint32_t pll_in_use = 0;

	if (ASIC_IS_DCE4(rdev)) {
		list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
			if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1450 1451 1452 1453 1454 1455 1456 1457 1458
				/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
				 * depending on the asic:
				 * DCE4: PPLL or ext clock
				 * DCE5: DCPLL or ext clock
				 *
				 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
				 * PPLL/DCPLL programming and only program the DP DTO for the
				 * crtc virtual pixel clock.
				 */
1459
				if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1460
					if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485
						return ATOM_PPLL_INVALID;
				}
			}
		}

		/* otherwise, pick one of the plls */
		list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
			struct radeon_crtc *radeon_test_crtc;

			if (crtc == test_crtc)
				continue;

			radeon_test_crtc = to_radeon_crtc(test_crtc);
			if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
			    (radeon_test_crtc->pll_id <= ATOM_PPLL2))
				pll_in_use |= (1 << radeon_test_crtc->pll_id);
		}
		if (!(pll_in_use & 1))
			return ATOM_PPLL1;
		return ATOM_PPLL2;
	} else
		return radeon_crtc->crtc_id;

}

1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503
void radeon_atom_dcpll_init(struct radeon_device *rdev)
{
	/* always set DCPLL */
	if (ASIC_IS_DCE4(rdev)) {
		struct radeon_atom_ss ss;
		bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
								   ASIC_INTERNAL_SS_ON_DCPLL,
								   rdev->clock.default_dispclk);
		if (ss_enabled)
			atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
		/* XXX: DCE5, make sure voltage, dispclk is high enough */
		atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);
		if (ss_enabled)
			atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
	}

}

1504 1505 1506 1507 1508 1509 1510 1511
int atombios_crtc_mode_set(struct drm_crtc *crtc,
			   struct drm_display_mode *mode,
			   struct drm_display_mode *adjusted_mode,
			   int x, int y, struct drm_framebuffer *old_fb)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
	struct drm_device *dev = crtc->dev;
	struct radeon_device *rdev = dev->dev_private;
1512 1513
	struct drm_encoder *encoder;
	bool is_tvcv = false;
1514

1515 1516 1517 1518 1519 1520 1521 1522 1523
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
		/* find tv std */
		if (encoder->crtc == crtc) {
			struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
			if (radeon_encoder->active_device &
			    (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
				is_tvcv = true;
		}
	}
1524 1525 1526

	atombios_crtc_set_pll(crtc, adjusted_mode);

1527
	if (ASIC_IS_DCE4(rdev))
1528
		atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1529 1530 1531 1532 1533 1534
	else if (ASIC_IS_AVIVO(rdev)) {
		if (is_tvcv)
			atombios_crtc_set_timing(crtc, adjusted_mode);
		else
			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
	} else {
1535
		atombios_crtc_set_timing(crtc, adjusted_mode);
1536 1537
		if (radeon_crtc->crtc_id == 0)
			atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1538
		radeon_legacy_atom_fixup(crtc);
1539
	}
1540
	atombios_crtc_set_base(crtc, x, y, old_fb);
1541 1542
	atombios_overscan_setup(crtc, mode, adjusted_mode);
	atombios_scaler_setup(crtc);
1543 1544 1545 1546 1547 1548 1549
	return 0;
}

static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
				     struct drm_display_mode *mode,
				     struct drm_display_mode *adjusted_mode)
{
1550 1551
	if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
		return false;
1552 1553 1554 1555 1556
	return true;
}

static void atombios_crtc_prepare(struct drm_crtc *crtc)
{
1557 1558 1559 1560 1561
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

	/* pick pll */
	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);

1562
	atombios_lock_crtc(crtc, ATOM_ENABLE);
1563
	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1564 1565 1566 1567 1568
}

static void atombios_crtc_commit(struct drm_crtc *crtc)
{
	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1569
	atombios_lock_crtc(crtc, ATOM_DISABLE);
1570 1571
}

1572 1573 1574
static void atombios_crtc_disable(struct drm_crtc *crtc)
{
	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1575 1576
	struct radeon_atom_ss ss;

1577 1578 1579 1580 1581 1582 1583
	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);

	switch (radeon_crtc->pll_id) {
	case ATOM_PPLL1:
	case ATOM_PPLL2:
		/* disable the ppll */
		atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1584
					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1585 1586 1587 1588 1589 1590 1591
		break;
	default:
		break;
	}
	radeon_crtc->pll_id = -1;
}

1592 1593 1594 1595 1596
static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
	.dpms = atombios_crtc_dpms,
	.mode_fixup = atombios_crtc_mode_fixup,
	.mode_set = atombios_crtc_mode_set,
	.mode_set_base = atombios_crtc_set_base,
1597
	.mode_set_base_atomic = atombios_crtc_set_base_atomic,
1598 1599
	.prepare = atombios_crtc_prepare,
	.commit = atombios_crtc_commit,
1600
	.load_lut = radeon_crtc_load_lut,
1601
	.disable = atombios_crtc_disable,
1602 1603 1604 1605 1606
};

void radeon_atombios_init_crtc(struct drm_device *dev,
			       struct radeon_crtc *radeon_crtc)
{
1607 1608 1609 1610 1611 1612
	struct radeon_device *rdev = dev->dev_private;

	if (ASIC_IS_DCE4(rdev)) {
		switch (radeon_crtc->crtc_id) {
		case 0:
		default:
1613
			radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1614 1615
			break;
		case 1:
1616
			radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1617 1618
			break;
		case 2:
1619
			radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1620 1621
			break;
		case 3:
1622
			radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1623 1624
			break;
		case 4:
1625
			radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1626 1627
			break;
		case 5:
1628
			radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1629 1630 1631 1632 1633 1634 1635 1636 1637 1638
			break;
		}
	} else {
		if (radeon_crtc->crtc_id == 1)
			radeon_crtc->crtc_offset =
				AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
		else
			radeon_crtc->crtc_offset = 0;
	}
	radeon_crtc->pll_id = -1;
1639 1640
	drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
}