pci.c 14.1 KB
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/*
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 * arch/arm/mach-orion5x/pci.c
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 *
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 * PCI and PCIe functions for Marvell Orion System On Chip
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 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
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 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
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 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/pci.h>
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#include <linux/mbus.h>
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#include <asm/mach/pci.h>
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#include <asm/plat-orion/pcie.h>
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#include "common.h"

/*****************************************************************************
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 * Orion has one PCIe controller and one PCI controller.
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 *
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 * Note1: The local PCIe bus number is '0'. The local PCI bus number
 * follows the scanned PCIe bridged busses, if any.
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 *
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 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
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 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
 * device bus, Orion registers, etc. However this code only enable the
 * access to DDR banks.
 ****************************************************************************/


/*****************************************************************************
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 * PCIe controller
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 ****************************************************************************/
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#define PCIE_BASE	((void __iomem *)ORION5X_PCIE_VIRT_BASE)
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void __init orion5x_pcie_id(u32 *dev, u32 *rev)
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{
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	*dev = orion_pcie_dev_id(PCIE_BASE);
	*rev = orion_pcie_rev(PCIE_BASE);
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}

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static int pcie_valid_config(int bus, int dev)
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{
	/*
	 * Don't go out when trying to access --
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	 * 1. nonexisting device on local bus
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	 * 2. where there's no device connected (no link)
	 */
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	if (bus == 0 && dev == 0)
		return 1;
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	if (!orion_pcie_link_up(PCIE_BASE))
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		return 0;

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	if (bus == 0 && dev != 1)
		return 0;

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	return 1;
}

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/*
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 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
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 * and then reading the PCIE_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
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static DEFINE_SPINLOCK(orion5x_pcie_lock);
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static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
			int size, u32 *val)
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{
	unsigned long flags;
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	int ret;
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	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
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		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

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	spin_lock_irqsave(&orion5x_pcie_lock, flags);
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	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
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	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
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	return ret;
}
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static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
			   int where, int size, u32 *val)
{
	int ret;
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	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
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	/*
	 * We only support access to the non-extended configuration
	 * space when using the WA access method (or we would have to
	 * sacrifice 256M of CPU virtual address space.)
	 */
	if (where >= 0x100) {
		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}
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	ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
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				    bus, devfn, where, size, val);
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	return ret;
}
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static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
			int where, int size, u32 val)
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{
	unsigned long flags;
	int ret;

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	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
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		return PCIBIOS_DEVICE_NOT_FOUND;

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	spin_lock_irqsave(&orion5x_pcie_lock, flags);
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	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
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	spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
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	return ret;
}

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static struct pci_ops pcie_ops = {
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	.read = pcie_rd_conf,
	.write = pcie_wr_conf,
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};


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static int __init pcie_setup(struct pci_sys_data *sys)
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{
	struct resource *res;
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	int dev;
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	/*
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	 * Generic PCIe unit setup.
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	 */
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	orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
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	/*
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	 * Check whether to apply Orion-1/Orion-NAS PCIe config
	 * read transaction workaround.
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	 */
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	dev = orion_pcie_dev_id(PCIE_BASE);
	if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
		printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
				   "read transaction workaround\n");
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		orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
					  ORION5X_PCIE_WA_SIZE);
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		pcie_ops.read = pcie_rd_conf_wa;
	}
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	/*
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	 * Request resources.
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	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
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		panic("pcie_setup unable to alloc resources");
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	/*
	 * IORESOURCE_IO
	 */
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	res[0].name = "PCIe I/O Space";
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	res[0].flags = IORESOURCE_IO;
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	res[0].start = ORION5X_PCIE_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
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	if (request_resource(&ioport_resource, &res[0]))
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		panic("Request PCIe IO resource failed\n");
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	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
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	res[1].name = "PCIe Memory Space";
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	res[1].flags = IORESOURCE_MEM;
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	res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
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	if (request_resource(&iomem_resource, &res[1]))
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		panic("Request PCIe Memory resource failed\n");
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	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}

/*****************************************************************************
 * PCI controller
 ****************************************************************************/
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#define PCI_MODE		ORION5X_PCI_REG(0xd00)
#define PCI_CMD			ORION5X_PCI_REG(0xc00)
#define PCI_P2P_CONF		ORION5X_PCI_REG(0x1d14)
#define PCI_CONF_ADDR		ORION5X_PCI_REG(0xc78)
#define PCI_CONF_DATA		ORION5X_PCI_REG(0xc7c)
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/*
 * PCI_MODE bits
 */
#define PCI_MODE_64BIT			(1 << 2)
#define PCI_MODE_PCIX			((1 << 4) | (1 << 5))

/*
 * PCI_CMD bits
 */
#define PCI_CMD_HOST_REORDER		(1 << 29)

/*
 * PCI_P2P_CONF bits
 */
#define PCI_P2P_BUS_OFFS		16
#define PCI_P2P_BUS_MASK		(0xff << PCI_P2P_BUS_OFFS)
#define PCI_P2P_DEV_OFFS		24
#define PCI_P2P_DEV_MASK		(0x1f << PCI_P2P_DEV_OFFS)

/*
 * PCI_CONF_ADDR bits
 */
#define PCI_CONF_REG(reg)		((reg) & 0xfc)
#define PCI_CONF_FUNC(func)		(((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev)		(((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus)		(((bus) & 0xff) << 16)
#define PCI_CONF_ADDR_EN		(1 << 31)

/*
 * Internal configuration space
 */
#define PCI_CONF_FUNC_STAT_CMD		0
#define PCI_CONF_REG_STAT_CMD		4
#define PCIX_STAT			0x64
#define PCIX_STAT_BUS_OFFS		8
#define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)

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/*
 * PCI Address Decode Windows registers
 */
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#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
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				 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
#define PCI_BAR_REMAP_DDR_CS(n)	(((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
				 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
				 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
				 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
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#define PCI_BAR_ENABLE		ORION5X_PCI_REG(0xc3c)
#define PCI_ADDR_DECODE_CTRL	ORION5X_PCI_REG(0xd3c)
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/*
 * PCI configuration helpers for BAR settings
 */
#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)

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/*
 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 * and then reading the PCI_CONF_DATA register. Need to make sure these
 * transactions are atomic.
 */
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static DEFINE_SPINLOCK(orion5x_pci_lock);
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static int orion5x_pci_local_bus_nr(void)
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{
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	u32 conf = orion5x_read(PCI_P2P_CONF);
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	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
}

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static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
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					u32 where, u32 size, u32 *val)
{
	unsigned long flags;
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	spin_lock_irqsave(&orion5x_pci_lock, flags);
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	orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
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			PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
			PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);

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	*val = orion5x_read(PCI_CONF_DATA);
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	if (size == 1)
		*val = (*val >> (8*(where & 0x3))) & 0xff;
	else if (size == 2)
		*val = (*val >> (8*(where & 0x3))) & 0xffff;

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	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
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	return PCIBIOS_SUCCESSFUL;
}

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static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
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					u32 where, u32 size, u32 val)
{
	unsigned long flags;
	int ret = PCIBIOS_SUCCESSFUL;

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	spin_lock_irqsave(&orion5x_pci_lock, flags);
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	orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) |
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			PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
			PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN);

	if (size == 4) {
		__raw_writel(val, PCI_CONF_DATA);
	} else if (size == 2) {
		__raw_writew(val, PCI_CONF_DATA + (where & 0x3));
	} else if (size == 1) {
		__raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
	} else {
		ret = PCIBIOS_BAD_REGISTER_NUMBER;
	}

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	spin_unlock_irqrestore(&orion5x_pci_lock, flags);
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	return ret;
}

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static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
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				int where, int size, u32 *val)
{
	/*
	 * Don't go out for local device
	 */
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	if (bus->number == orion5x_pci_local_bus_nr() &&
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	    PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
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		*val = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

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	return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
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					PCI_FUNC(devfn), where, size, val);
}

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static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
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				int where, int size, u32 val)
{
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	if (bus->number == orion5x_pci_local_bus_nr() &&
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	    PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
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		return PCIBIOS_DEVICE_NOT_FOUND;

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	return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
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					PCI_FUNC(devfn), where, size, val);
}

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static struct pci_ops pci_ops = {
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	.read = orion5x_pci_rd_conf,
	.write = orion5x_pci_wr_conf,
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};

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static void __init orion5x_pci_set_bus_nr(int nr)
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{
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	u32 p2p = orion5x_read(PCI_P2P_CONF);
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	if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) {
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		/*
		 * PCI-X mode
		 */
		u32 pcix_status, bus, dev;
		bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
		dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
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		orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
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		pcix_status &= ~PCIX_STAT_BUS_MASK;
		pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
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		orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
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	} else {
		/*
		 * PCI Conventional mode
		 */
		p2p &= ~PCI_P2P_BUS_MASK;
		p2p |= (nr << PCI_P2P_BUS_OFFS);
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		orion5x_write(PCI_P2P_CONF, p2p);
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	}
}

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static void __init orion5x_pci_master_slave_enable(void)
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{
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	int bus_nr, func, reg;
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	u32 val;
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	bus_nr = orion5x_pci_local_bus_nr();
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	func = PCI_CONF_FUNC_STAT_CMD;
	reg = PCI_CONF_REG_STAT_CMD;
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	orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
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	val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
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}

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static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
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{
	u32 win_enable;
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	int bus;
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	int i;

	/*
	 * First, disable windows.
	 */
	win_enable = 0xffffffff;
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	orion5x_write(PCI_BAR_ENABLE, win_enable);
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	/*
	 * Setup windows for DDR banks.
	 */
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	bus = orion5x_pci_local_bus_nr();
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	for (i = 0; i < dram->num_cs; i++) {
		struct mbus_dram_window *cs = dram->cs + i;
		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
		u32 reg;
		u32 val;

		/*
		 * Write DRAM bank base address register.
		 */
		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
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		orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
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		val = (cs->base & 0xfffff000) | (val & 0xfff);
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		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
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		/*
		 * Write DRAM bank size register.
		 */
		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
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		orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
		orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
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				(cs->size - 1) & 0xfffff000);
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		orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
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				cs->base & 0xfffff000);

		/*
		 * Enable decode window for this chip select.
		 */
		win_enable &= ~(1 << cs->cs_index);
	}

	/*
	 * Re-enable decode windows.
	 */
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	orion5x_write(PCI_BAR_ENABLE, win_enable);
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	/*
	 * Disable automatic update of address remaping when writing to BARs.
	 */
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	orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
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}

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static int __init pci_setup(struct pci_sys_data *sys)
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{
	struct resource *res;

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	/*
	 * Point PCI unit MBUS decode windows to DRAM space.
	 */
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	orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
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	/*
	 * Master + Slave enable
	 */
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	orion5x_pci_master_slave_enable();
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	/*
	 * Force ordering
	 */
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	orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
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	/*
	 * Request resources
	 */
	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
	if (!res)
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		panic("pci_setup unable to alloc resources");
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	/*
	 * IORESOURCE_IO
	 */
	res[0].name = "PCI I/O Space";
	res[0].flags = IORESOURCE_IO;
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	res[0].start = ORION5X_PCI_IO_BUS_BASE;
	res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
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	if (request_resource(&ioport_resource, &res[0]))
		panic("Request PCI IO resource failed\n");
	sys->resource[0] = &res[0];

	/*
	 * IORESOURCE_MEM
	 */
	res[1].name = "PCI Memory Space";
	res[1].flags = IORESOURCE_MEM;
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	res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
	res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
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	if (request_resource(&iomem_resource, &res[1]))
		panic("Request PCI Memory resource failed\n");
	sys->resource[1] = &res[1];

	sys->resource[2] = NULL;
	sys->io_offset = 0;

	return 1;
}


/*****************************************************************************
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 * General PCIe + PCI
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 ****************************************************************************/
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static void __devinit rc_pci_fixup(struct pci_dev *dev)
{
	/*
	 * Prevent enumeration of root complex.
	 */
	if (dev->bus->parent == NULL && dev->devfn == 0) {
		int i;

		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
			dev->resource[i].start = 0;
			dev->resource[i].end   = 0;
			dev->resource[i].flags = 0;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);

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int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
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{
	int ret = 0;

	if (nr == 0) {
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		orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
		ret = pcie_setup(sys);
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	} else if (nr == 1) {
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		orion5x_pci_set_bus_nr(sys->busnr);
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		ret = pci_setup(sys);
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	}

	return ret;
}

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struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
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{
	struct pci_bus *bus;

	if (nr == 0) {
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		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
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	} else if (nr == 1) {
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		bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
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	} else {
		bus = NULL;
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		BUG();
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	}

	return bus;
}
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int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	int bus = dev->bus->number;

	/*
	 * PCIe endpoint?
	 */
	if (bus < orion5x_pci_local_bus_nr())
		return IRQ_ORION5X_PCIE0_INT;

	return -1;
}