exynos_drm_fimd.c 25.7 KB
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/* exynos_drm_fimd.c
 *
 * Copyright (C) 2011 Samsung Electronics Co.Ltd
 * Authors:
 *	Joonyoung Shim <jy0922.shim@samsung.com>
 *	Inki Dae <inki.dae@samsung.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */
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#include <drm/drmP.h>
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#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/component.h>
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#include <video/of_display_timing.h>
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#include <video/of_videomode.h>
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#include <video/samsung_fimd.h>
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#include <drm/exynos_drm.h>

#include "exynos_drm_drv.h"
#include "exynos_drm_fbdev.h"
#include "exynos_drm_crtc.h"
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#include "exynos_drm_iommu.h"
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/*
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 * FIMD stands for Fully Interactive Mobile Display and
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 * as a display controller, it transfers contents drawn on memory
 * to a LCD Panel through Display Interfaces such as RGB or
 * CPU Interface.
 */

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#define FIMD_DEFAULT_FRAMERATE 60
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#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
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/* position control register for hardware window 0, 2 ~ 4.*/
#define VIDOSD_A(win)		(VIDOSD_BASE + 0x00 + (win) * 16)
#define VIDOSD_B(win)		(VIDOSD_BASE + 0x04 + (win) * 16)
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/*
 * size control register for hardware windows 0 and alpha control register
 * for hardware windows 1 ~ 4
 */
#define VIDOSD_C(win)		(VIDOSD_BASE + 0x08 + (win) * 16)
/* size control register for hardware windows 1 ~ 2. */
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#define VIDOSD_D(win)		(VIDOSD_BASE + 0x0C + (win) * 16)

#define VIDWx_BUF_START(win, buf)	(VIDW_BUF_START(buf) + (win) * 8)
#define VIDWx_BUF_END(win, buf)		(VIDW_BUF_END(buf) + (win) * 8)
#define VIDWx_BUF_SIZE(win, buf)	(VIDW_BUF_SIZE(buf) + (win) * 4)

/* color key control register for hardware window 1 ~ 4. */
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#define WKEYCON0_BASE(x)		((WKEYCON0 + 0x140) + ((x - 1) * 8))
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/* color key value register for hardware window 1 ~ 4. */
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#define WKEYCON1_BASE(x)		((WKEYCON1 + 0x140) + ((x - 1) * 8))
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/* FIMD has totally five hardware windows. */
#define WINDOWS_NR	5

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#define get_fimd_manager(mgr)	platform_get_drvdata(to_platform_device(dev))
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struct fimd_driver_data {
	unsigned int timing_base;
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	unsigned int has_shadowcon:1;
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	unsigned int has_clksel:1;
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	unsigned int has_limited_fmt:1;
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};

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static struct fimd_driver_data s3c64xx_fimd_driver_data = {
	.timing_base = 0x0,
	.has_clksel = 1,
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	.has_limited_fmt = 1,
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};

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static struct fimd_driver_data exynos4_fimd_driver_data = {
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	.timing_base = 0x0,
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	.has_shadowcon = 1,
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};

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static struct fimd_driver_data exynos5_fimd_driver_data = {
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	.timing_base = 0x20000,
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	.has_shadowcon = 1,
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};

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struct fimd_win_data {
	unsigned int		offset_x;
	unsigned int		offset_y;
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	unsigned int		ovl_width;
	unsigned int		ovl_height;
	unsigned int		fb_width;
	unsigned int		fb_height;
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	unsigned int		bpp;
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	unsigned int		pixel_format;
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	dma_addr_t		dma_addr;
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	unsigned int		buf_offsize;
	unsigned int		line_size;	/* bytes */
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	bool			enabled;
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	bool			resume;
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};

struct fimd_context {
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	struct device			*dev;
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	struct drm_device		*drm_dev;
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	struct clk			*bus_clk;
	struct clk			*lcd_clk;
	void __iomem			*regs;
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	struct drm_display_mode		mode;
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	struct fimd_win_data		win_data[WINDOWS_NR];
	unsigned int			default_win;
	unsigned long			irq_flags;
	u32				vidcon1;
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	bool				suspended;
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	int				pipe;
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	wait_queue_head_t		wait_vsync_queue;
	atomic_t			wait_vsync_event;
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	struct exynos_drm_panel_info panel;
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	struct fimd_driver_data *driver_data;
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	struct exynos_drm_display *display;
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};

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static const struct of_device_id fimd_driver_dt_match[] = {
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	{ .compatible = "samsung,s3c6400-fimd",
	  .data = &s3c64xx_fimd_driver_data },
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	{ .compatible = "samsung,exynos4210-fimd",
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	  .data = &exynos4_fimd_driver_data },
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	{ .compatible = "samsung,exynos5250-fimd",
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	  .data = &exynos5_fimd_driver_data },
	{},
};

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static inline struct fimd_driver_data *drm_fimd_get_driver_data(
	struct platform_device *pdev)
{
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	const struct of_device_id *of_id =
			of_match_device(fimd_driver_dt_match, &pdev->dev);

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	return (struct fimd_driver_data *)of_id->data;
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}

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static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;

	if (ctx->suspended)
		return;

	atomic_set(&ctx->wait_vsync_event, 1);

	/*
	 * wait for FIMD to signal VSYNC interrupt or return after
	 * timeout which is set to 50ms (refresh rate of 20).
	 */
	if (!wait_event_timeout(ctx->wait_vsync_queue,
				!atomic_read(&ctx->wait_vsync_event),
				HZ/20))
		DRM_DEBUG_KMS("vblank wait timed out.\n");
}


static void fimd_clear_channel(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;
	int win, ch_enabled = 0;

	DRM_DEBUG_KMS("%s\n", __FILE__);

	/* Check if any channel is enabled. */
	for (win = 0; win < WINDOWS_NR; win++) {
		u32 val = readl(ctx->regs + SHADOWCON);
		if (val & SHADOWCON_CHx_ENABLE(win)) {
			val &= ~SHADOWCON_CHx_ENABLE(win);
			writel(val, ctx->regs + SHADOWCON);
			ch_enabled = 1;
		}
	}

	/* Wait for vsync, as disable channel takes effect at next vsync */
	if (ch_enabled)
		fimd_wait_for_vblank(mgr);
}

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static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
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			struct drm_device *drm_dev)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	struct exynos_drm_private *priv;
	priv = drm_dev->dev_private;
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	mgr->drm_dev = ctx->drm_dev = drm_dev;
	mgr->pipe = ctx->pipe = priv->pipe++;
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	/*
	 * enable drm irq mode.
	 * - with irq_enabled = true, we can use the vblank feature.
	 *
	 * P.S. note that we wouldn't use drm irq handler but
	 *	just specific driver own one instead because
	 *	drm framework supports only one irq handler.
	 */
	drm_dev->irq_enabled = true;
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	/*
	 * with vblank_disable_allowed = true, vblank interrupt will be disabled
	 * by drm timer once a current process gives up ownership of
	 * vblank event.(after drm_vblank_put function is called)
	 */
	drm_dev->vblank_disable_allowed = true;
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	/* attach this sub driver to iommu mapping if supported. */
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	if (is_drm_iommu_supported(ctx->drm_dev)) {
		/*
		 * If any channel is already active, iommu will throw
		 * a PAGE FAULT when enabled. So clear any channel if enabled.
		 */
		fimd_clear_channel(mgr);
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		drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
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	}
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	return 0;
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}

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static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	/* detach this sub driver from iommu mapping if supported. */
	if (is_drm_iommu_supported(ctx->drm_dev))
		drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
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}

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static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
		const struct drm_display_mode *mode)
{
	unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
	u32 clkdiv;

	/* Find the clock divider value that gets us closest to ideal_clk */
	clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);

	return (clkdiv < 0x100) ? clkdiv : 0xff;
}

static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
		const struct drm_display_mode *mode,
		struct drm_display_mode *adjusted_mode)
{
	if (adjusted_mode->vrefresh == 0)
		adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;

	return true;
}

static void fimd_mode_set(struct exynos_drm_manager *mgr,
		const struct drm_display_mode *in_mode)
{
	struct fimd_context *ctx = mgr->ctx;

	drm_mode_copy(&ctx->mode, in_mode);
}

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static void fimd_commit(struct exynos_drm_manager *mgr)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	struct drm_display_mode *mode = &ctx->mode;
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	struct fimd_driver_data *driver_data;
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	u32 val, clkdiv, vidcon1;
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	int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
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	driver_data = ctx->driver_data;
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	if (ctx->suspended)
		return;

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	/* nothing to do if we haven't set the mode yet */
	if (mode->htotal == 0 || mode->vtotal == 0)
		return;

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	/* setup polarity values */
	vidcon1 = ctx->vidcon1;
	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
		vidcon1 |= VIDCON1_INV_VSYNC;
	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
		vidcon1 |= VIDCON1_INV_HSYNC;
	writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
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	/* setup vertical timing values. */
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	vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
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	vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
	vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
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	val = VIDTCON0_VBPD(vbpd - 1) |
		VIDTCON0_VFPD(vfpd - 1) |
		VIDTCON0_VSPW(vsync_len - 1);
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	writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
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	/* setup horizontal timing values.  */
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	hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
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	hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
	hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
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	val = VIDTCON1_HBPD(hbpd - 1) |
		VIDTCON1_HFPD(hfpd - 1) |
		VIDTCON1_HSPW(hsync_len - 1);
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	writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
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	/* setup horizontal and vertical display size. */
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	val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
	       VIDTCON2_HOZVAL(mode->hdisplay - 1) |
	       VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
	       VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
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	writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
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	/*
	 * fields of register with prefix '_F' would be updated
	 * at vsync(same as dma start)
	 */
	val = VIDCON0_ENVID | VIDCON0_ENVID_F;
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	if (ctx->driver_data->has_clksel)
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		val |= VIDCON0_CLKSEL_LCD;

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	clkdiv = fimd_calc_clkdiv(ctx, mode);
	if (clkdiv > 1)
		val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
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	writel(val, ctx->regs + VIDCON0);
}

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static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	u32 val;

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	if (ctx->suspended)
		return -EPERM;

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	if (!test_and_set_bit(0, &ctx->irq_flags)) {
		val = readl(ctx->regs + VIDINTCON0);

		val |= VIDINTCON0_INT_ENABLE;
		val |= VIDINTCON0_INT_FRAME;

		val &= ~VIDINTCON0_FRAMESEL0_MASK;
		val |= VIDINTCON0_FRAMESEL0_VSYNC;
		val &= ~VIDINTCON0_FRAMESEL1_MASK;
		val |= VIDINTCON0_FRAMESEL1_NONE;

		writel(val, ctx->regs + VIDINTCON0);
	}

	return 0;
}

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static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	u32 val;

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	if (ctx->suspended)
		return;

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	if (test_and_clear_bit(0, &ctx->irq_flags)) {
		val = readl(ctx->regs + VIDINTCON0);

		val &= ~VIDINTCON0_INT_FRAME;
		val &= ~VIDINTCON0_INT_ENABLE;

		writel(val, ctx->regs + VIDINTCON0);
	}
}

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static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
			struct exynos_drm_overlay *overlay)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	struct fimd_win_data *win_data;
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	int win;
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	unsigned long offset;
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	if (!overlay) {
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		DRM_ERROR("overlay is NULL\n");
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		return;
	}

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	win = overlay->zpos;
	if (win == DEFAULT_ZPOS)
		win = ctx->default_win;

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	if (win < 0 || win >= WINDOWS_NR)
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		return;

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	offset = overlay->fb_x * (overlay->bpp >> 3);
	offset += overlay->fb_y * overlay->pitch;

	DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);

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	win_data = &ctx->win_data[win];
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	win_data->offset_x = overlay->crtc_x;
	win_data->offset_y = overlay->crtc_y;
	win_data->ovl_width = overlay->crtc_width;
	win_data->ovl_height = overlay->crtc_height;
	win_data->fb_width = overlay->fb_width;
	win_data->fb_height = overlay->fb_height;
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	win_data->dma_addr = overlay->dma_addr[0] + offset;
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	win_data->bpp = overlay->bpp;
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	win_data->pixel_format = overlay->pixel_format;
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	win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
				(overlay->bpp >> 3);
	win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);

	DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
			win_data->offset_x, win_data->offset_y);
	DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
			win_data->ovl_width, win_data->ovl_height);
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	DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
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	DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
			overlay->fb_width, overlay->crtc_width);
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}

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static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
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{
	struct fimd_win_data *win_data = &ctx->win_data[win];
	unsigned long val;

	val = WINCONx_ENWIN;

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	/*
	 * In case of s3c64xx, window 0 doesn't support alpha channel.
	 * So the request format is ARGB8888 then change it to XRGB8888.
	 */
	if (ctx->driver_data->has_limited_fmt && !win) {
		if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
			win_data->pixel_format = DRM_FORMAT_XRGB8888;
	}

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	switch (win_data->pixel_format) {
	case DRM_FORMAT_C8:
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		val |= WINCON0_BPPMODE_8BPP_PALETTE;
		val |= WINCONx_BURSTLEN_8WORD;
		val |= WINCONx_BYTSWP;
		break;
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	case DRM_FORMAT_XRGB1555:
		val |= WINCON0_BPPMODE_16BPP_1555;
		val |= WINCONx_HAWSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
	case DRM_FORMAT_RGB565:
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		val |= WINCON0_BPPMODE_16BPP_565;
		val |= WINCONx_HAWSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
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	case DRM_FORMAT_XRGB8888:
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		val |= WINCON0_BPPMODE_24BPP_888;
		val |= WINCONx_WSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
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	case DRM_FORMAT_ARGB8888:
		val |= WINCON1_BPPMODE_25BPP_A1888
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			| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
		val |= WINCONx_WSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
	default:
		DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");

		val |= WINCON0_BPPMODE_24BPP_888;
		val |= WINCONx_WSWP;
		val |= WINCONx_BURSTLEN_16WORD;
		break;
	}

	DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);

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	/*
	 * In case of exynos, setting dma-burst to 16Word causes permanent
	 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
	 * switching which is based on overlay size is not recommended as
	 * overlay size varies alot towards the end of the screen and rapid
	 * movement causes unstable DMA which results into iommu crash/tear.
	 */

	if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
		val &= ~WINCONx_BURSTLEN_MASK;
		val |= WINCONx_BURSTLEN_4WORD;
	}

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	writel(val, ctx->regs + WINCON(win));
}

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static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
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{
	unsigned int keycon0 = 0, keycon1 = 0;

	keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
			WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);

	keycon1 = WxKEYCON1_COLVAL(0xffffffff);

	writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
}

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/**
 * shadow_protect_win() - disable updating values from shadow registers at vsync
 *
 * @win: window to protect registers for
 * @protect: 1 to protect (disable updates)
 */
static void fimd_shadow_protect_win(struct fimd_context *ctx,
							int win, bool protect)
{
	u32 reg, bits, val;

	if (ctx->driver_data->has_shadowcon) {
		reg = SHADOWCON;
		bits = SHADOWCON_WINx_PROTECT(win);
	} else {
		reg = PRTCON;
		bits = PRTCON_PROTECT;
	}

	val = readl(ctx->regs + reg);
	if (protect)
		val |= bits;
	else
		val &= ~bits;
	writel(val, ctx->regs + reg);
}

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static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
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{
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	struct fimd_context *ctx = mgr->ctx;
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	struct fimd_win_data *win_data;
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	int win = zpos;
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	unsigned long val, alpha, size;
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	unsigned int last_x;
	unsigned int last_y;
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	if (ctx->suspended)
		return;

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	if (win == DEFAULT_ZPOS)
		win = ctx->default_win;

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	if (win < 0 || win >= WINDOWS_NR)
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		return;

	win_data = &ctx->win_data[win];

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	/* If suspended, enable this on resume */
	if (ctx->suspended) {
		win_data->resume = true;
		return;
	}

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	/*
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	 * SHADOWCON/PRTCON register is used for enabling timing.
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	 *
	 * for example, once only width value of a register is set,
	 * if the dma is started then fimd hardware could malfunction so
	 * with protect window setting, the register fields with prefix '_F'
	 * wouldn't be updated at vsync also but updated once unprotect window
	 * is set.
	 */

	/* protect windows */
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	fimd_shadow_protect_win(ctx, win, true);
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	/* buffer start address */
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	val = (unsigned long)win_data->dma_addr;
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	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));

	/* buffer end address */
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	size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
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	val = (unsigned long)(win_data->dma_addr + size);
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	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));

	DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
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			(unsigned long)win_data->dma_addr, val, size);
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	DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
			win_data->ovl_width, win_data->ovl_height);
591 592 593

	/* buffer size */
	val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
594 595 596
		VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
		VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
		VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
597 598 599 600
	writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));

	/* OSD position */
	val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
601 602 603
		VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
		VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
		VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
604 605
	writel(val, ctx->regs + VIDOSD_A(win));

606 607 608 609 610 611 612
	last_x = win_data->offset_x + win_data->ovl_width;
	if (last_x)
		last_x--;
	last_y = win_data->offset_y + win_data->ovl_height;
	if (last_y)
		last_y--;

613 614 615
	val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
		VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);

616 617
	writel(val, ctx->regs + VIDOSD_B(win));

618
	DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
619
			win_data->offset_x, win_data->offset_y, last_x, last_y);
620 621 622 623 624 625 626 627 628 629 630 631 632 633 634

	/* hardware window 0 doesn't support alpha channel. */
	if (win != 0) {
		/* OSD alpha */
		alpha = VIDISD14C_ALPHA1_R(0xf) |
			VIDISD14C_ALPHA1_G(0xf) |
			VIDISD14C_ALPHA1_B(0xf);

		writel(alpha, ctx->regs + VIDOSD_C(win));
	}

	/* OSD size */
	if (win != 3 && win != 4) {
		u32 offset = VIDOSD_D(win);
		if (win == 0)
635
			offset = VIDOSD_C(win);
636
		val = win_data->ovl_width * win_data->ovl_height;
637 638 639 640 641
		writel(val, ctx->regs + offset);

		DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
	}

642
	fimd_win_set_pixfmt(ctx, win);
643 644 645

	/* hardware window 0 doesn't support color key. */
	if (win != 0)
646
		fimd_win_set_colkey(ctx, win);
647

648 649 650 651 652
	/* wincon */
	val = readl(ctx->regs + WINCON(win));
	val |= WINCONx_ENWIN;
	writel(val, ctx->regs + WINCON(win));

653
	/* Enable DMA channel and unprotect windows */
654 655 656 657 658 659 660
	fimd_shadow_protect_win(ctx, win, false);

	if (ctx->driver_data->has_shadowcon) {
		val = readl(ctx->regs + SHADOWCON);
		val |= SHADOWCON_CHx_ENABLE(win);
		writel(val, ctx->regs + SHADOWCON);
	}
661 662

	win_data->enabled = true;
663 664
}

665
static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
666
{
667
	struct fimd_context *ctx = mgr->ctx;
668
	struct fimd_win_data *win_data;
669
	int win = zpos;
670 671
	u32 val;

672 673 674
	if (win == DEFAULT_ZPOS)
		win = ctx->default_win;

675
	if (win < 0 || win >= WINDOWS_NR)
676 677
		return;

678 679
	win_data = &ctx->win_data[win];

680 681 682 683 684 685
	if (ctx->suspended) {
		/* do not resume this window*/
		win_data->resume = false;
		return;
	}

686
	/* protect windows */
687
	fimd_shadow_protect_win(ctx, win, true);
688 689 690 691 692 693 694

	/* wincon */
	val = readl(ctx->regs + WINCON(win));
	val &= ~WINCONx_ENWIN;
	writel(val, ctx->regs + WINCON(win));

	/* unprotect windows */
695 696 697 698 699 700 701
	if (ctx->driver_data->has_shadowcon) {
		val = readl(ctx->regs + SHADOWCON);
		val &= ~SHADOWCON_CHx_ENABLE(win);
		writel(val, ctx->regs + SHADOWCON);
	}

	fimd_shadow_protect_win(ctx, win, false);
702 703

	win_data->enabled = false;
704 705
}

706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758
static void fimd_window_suspend(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;
	struct fimd_win_data *win_data;
	int i;

	for (i = 0; i < WINDOWS_NR; i++) {
		win_data = &ctx->win_data[i];
		win_data->resume = win_data->enabled;
		if (win_data->enabled)
			fimd_win_disable(mgr, i);
	}
	fimd_wait_for_vblank(mgr);
}

static void fimd_window_resume(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;
	struct fimd_win_data *win_data;
	int i;

	for (i = 0; i < WINDOWS_NR; i++) {
		win_data = &ctx->win_data[i];
		win_data->enabled = win_data->resume;
		win_data->resume = false;
	}
}

static void fimd_apply(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;
	struct fimd_win_data *win_data;
	int i;

	for (i = 0; i < WINDOWS_NR; i++) {
		win_data = &ctx->win_data[i];
		if (win_data->enabled)
			fimd_win_commit(mgr, i);
	}

	fimd_commit(mgr);
}

static int fimd_poweron(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;
	int ret;

	if (!ctx->suspended)
		return 0;

	ctx->suspended = false;

759 760
	pm_runtime_get_sync(ctx->dev);

761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813
	ret = clk_prepare_enable(ctx->bus_clk);
	if (ret < 0) {
		DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
		goto bus_clk_err;
	}

	ret = clk_prepare_enable(ctx->lcd_clk);
	if  (ret < 0) {
		DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
		goto lcd_clk_err;
	}

	/* if vblank was enabled status, enable it again. */
	if (test_and_clear_bit(0, &ctx->irq_flags)) {
		ret = fimd_enable_vblank(mgr);
		if (ret) {
			DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
			goto enable_vblank_err;
		}
	}

	fimd_window_resume(mgr);

	fimd_apply(mgr);

	return 0;

enable_vblank_err:
	clk_disable_unprepare(ctx->lcd_clk);
lcd_clk_err:
	clk_disable_unprepare(ctx->bus_clk);
bus_clk_err:
	ctx->suspended = true;
	return ret;
}

static int fimd_poweroff(struct exynos_drm_manager *mgr)
{
	struct fimd_context *ctx = mgr->ctx;

	if (ctx->suspended)
		return 0;

	/*
	 * We need to make sure that all windows are disabled before we
	 * suspend that connector. Otherwise we might try to scan from
	 * a destroyed buffer later.
	 */
	fimd_window_suspend(mgr);

	clk_disable_unprepare(ctx->lcd_clk);
	clk_disable_unprepare(ctx->bus_clk);

814 815
	pm_runtime_put_sync(ctx->dev);

816 817 818 819
	ctx->suspended = true;
	return 0;
}

820 821
static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
{
822
	DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
823 824 825

	switch (mode) {
	case DRM_MODE_DPMS_ON:
826
		fimd_poweron(mgr);
827 828 829 830
		break;
	case DRM_MODE_DPMS_STANDBY:
	case DRM_MODE_DPMS_SUSPEND:
	case DRM_MODE_DPMS_OFF:
831
		fimd_poweroff(mgr);
832 833 834 835 836 837 838
		break;
	default:
		DRM_DEBUG_KMS("unspecified mode %d\n", mode);
		break;
	}
}

839 840
static struct exynos_drm_manager_ops fimd_manager_ops = {
	.dpms = fimd_dpms,
841 842
	.mode_fixup = fimd_mode_fixup,
	.mode_set = fimd_mode_set,
843 844 845 846 847 848 849
	.commit = fimd_commit,
	.enable_vblank = fimd_enable_vblank,
	.disable_vblank = fimd_disable_vblank,
	.wait_for_vblank = fimd_wait_for_vblank,
	.win_mode_set = fimd_win_mode_set,
	.win_commit = fimd_win_commit,
	.win_disable = fimd_win_disable,
850 851
};

852
static struct exynos_drm_manager fimd_manager = {
853 854
	.type = EXYNOS_DISPLAY_TYPE_LCD,
	.ops = &fimd_manager_ops,
855 856
};

857 858 859 860 861 862 863 864 865 866 867
static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
{
	struct fimd_context *ctx = (struct fimd_context *)dev_id;
	u32 val;

	val = readl(ctx->regs + VIDINTCON1);

	if (val & VIDINTCON1_INT_FRAME)
		/* VSYNC interrupt */
		writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);

868
	/* check the crtc is detached already from encoder */
869
	if (ctx->pipe < 0 || !ctx->drm_dev)
870
		goto out;
I
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871

872 873
	drm_handle_vblank(ctx->drm_dev, ctx->pipe);
	exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
874

875 876 877
	/* set wait vsync event to zero and wake up queue. */
	if (atomic_read(&ctx->wait_vsync_event)) {
		atomic_set(&ctx->wait_vsync_event, 0);
878
		wake_up(&ctx->wait_vsync_queue);
879
	}
880
out:
881 882 883
	return IRQ_HANDLED;
}

884
static int fimd_bind(struct device *dev, struct device *master, void *data)
885
{
886
	struct fimd_context *ctx = fimd_manager.ctx;
887
	struct drm_device *drm_dev = data;
888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922

	fimd_mgr_initialize(&fimd_manager, drm_dev);
	exynos_drm_crtc_create(&fimd_manager);
	if (ctx->display)
		exynos_drm_create_enc_conn(drm_dev, ctx->display);

	return 0;

}

static void fimd_unbind(struct device *dev, struct device *master,
			void *data)
{
	struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
	struct fimd_context *ctx = fimd_manager.ctx;
	struct drm_crtc *crtc = mgr->crtc;

	fimd_dpms(mgr, DRM_MODE_DPMS_OFF);

	if (ctx->display)
		exynos_dpi_remove(dev);

	fimd_mgr_remove(mgr);

	crtc->funcs->destroy(crtc);
}

static const struct component_ops fimd_component_ops = {
	.bind	= fimd_bind,
	.unbind = fimd_unbind,
};

static int fimd_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
923 924 925
	struct fimd_context *ctx;
	struct resource *res;
	int ret = -EINVAL;
926

927 928 929 930 931 932 933 934 935
	ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
					fimd_manager.type);
	if (ret)
		return ret;

	if (!dev->of_node) {
		ret = -ENODEV;
		goto err_del_component;
	}
936

937
	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
938 939 940 941
	if (!ctx) {
		ret = -ENOMEM;
		goto err_del_component;
	}
942

943
	ctx->dev = dev;
944
	ctx->suspended = true;
945

946 947 948 949
	if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
		ctx->vidcon1 |= VIDCON1_INV_VDEN;
	if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
		ctx->vidcon1 |= VIDCON1_INV_VCLK;
950

951 952 953
	ctx->bus_clk = devm_clk_get(dev, "fimd");
	if (IS_ERR(ctx->bus_clk)) {
		dev_err(dev, "failed to get bus clock\n");
954 955
		ret = PTR_ERR(ctx->bus_clk);
		goto err_del_component;
956 957 958 959 960
	}

	ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
	if (IS_ERR(ctx->lcd_clk)) {
		dev_err(dev, "failed to get lcd clock\n");
961 962
		ret = PTR_ERR(ctx->lcd_clk);
		goto err_del_component;
963
	}
964 965 966

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

967
	ctx->regs = devm_ioremap_resource(dev, res);
968 969 970 971
	if (IS_ERR(ctx->regs)) {
		ret = PTR_ERR(ctx->regs);
		goto err_del_component;
	}
972

973
	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
974 975
	if (!res) {
		dev_err(dev, "irq request failed.\n");
976 977
		ret = -ENXIO;
		goto err_del_component;
978 979
	}

980
	ret = devm_request_irq(dev, res->start, fimd_irq_handler,
981 982
							0, "drm_fimd", ctx);
	if (ret) {
983
		dev_err(dev, "irq request failed.\n");
984
		goto err_del_component;
985 986
	}

987
	ctx->driver_data = drm_fimd_get_driver_data(pdev);
988
	init_waitqueue_head(&ctx->wait_vsync_queue);
989
	atomic_set(&ctx->wait_vsync_event, 0);
990

991
	platform_set_drvdata(pdev, &fimd_manager);
992

993
	fimd_manager.ctx = ctx;
994

995 996 997
	ctx->display = exynos_dpi_probe(dev);
	if (IS_ERR(ctx->display))
		return PTR_ERR(ctx->display);
998 999 1000

	pm_runtime_enable(&pdev->dev);

1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
	ret = component_add(&pdev->dev, &fimd_component_ops);
	if (ret)
		goto err_disable_pm_runtime;

	return ret;

err_disable_pm_runtime:
	pm_runtime_disable(&pdev->dev);

err_del_component:
	exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
	return ret;
1013
}
1014

1015 1016
static int fimd_remove(struct platform_device *pdev)
{
1017
	pm_runtime_disable(&pdev->dev);
1018

1019 1020 1021
	component_del(&pdev->dev, &fimd_component_ops);
	exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);

1022
	return 0;
I
Inki Dae 已提交
1023 1024
}

1025
struct platform_driver fimd_driver = {
1026
	.probe		= fimd_probe,
1027
	.remove		= fimd_remove,
1028 1029 1030
	.driver		= {
		.name	= "exynos4-fb",
		.owner	= THIS_MODULE,
1031
		.of_match_table = fimd_driver_dt_match,
1032 1033
	},
};