- 24 2月, 2011 3 次提交
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由 Christophe Lyon 提交于
Now use the same algorithm as described in the ARM ARM. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Now use the same algorithm as described in the ARM ARM. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
These two constants will be used by helper functions such as recpe_f32 and rsqrte_f32. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 11 2月, 2011 3 次提交
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由 Peter Maydell 提交于
The Neon half-precision conversion operations (VCVT.F16.F32 and VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike the VFP versions (VCVTB and VCVTT). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Silence the NaNs that may result from half-precision conversion, as we do for the other conversions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Add a float16 type to softfloat, rather than using bits16 directly. Also add the missing functions float16_is_quiet_nan(), float16_is_signaling_nan() and float16_maybe_silence_nan(), which are needed for the float16 conversion routines. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 05 2月, 2011 2 次提交
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由 Peter Maydell 提交于
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Add a CPU feature flag for v7MP (the multiprocessing extensions); some instructions exist only for v7MP and not for the base v7 architecture. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 15 1月, 2011 4 次提交
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由 Peter Maydell 提交于
When translating the SRS instruction, handle the "store registers to stack of current mode" case in the helper function rather than inline. This means the generated code does not make assumptions about the current CPU mode which might not be valid when the TB is executed later. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
VSQRTS always uses the standard FPSCR value as it is a Neon instruction. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Add support to the ARM helper routines for a second fp_status value which should be used for operations which the ARM ARM indicates use "ARM standard floating-point arithmetic" rather than being controlled by the rounding/flush/NaN settings in the FPSCR. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
The implementation of the ARM VRSQRTS instruction (which calculates (3 - op1 * op2) / 2) was missing the division operation. It also did not handle the special cases of (0,inf) and (inf,0). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 07 1月, 2011 2 次提交
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由 Peter Maydell 提交于
Wire up the new softfloat support for flushing input denormals to zero on ARM. The FPSCR FZ bit enables flush-to-zero for both inputs and outputs, but the reporting of when inputs are flushed to zero is via a separate IDC bit rather than the UFC (underflow) bit used when output denormals are flushed to zero. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
When handling a write to the ARM FPSCR, set the softfloat cumulative exception flags from the cumulative flags in the FPSCR, not the exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host will only look at the correct bits anyway. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 28 12月, 2010 3 次提交
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由 Juha Riihimäki 提交于
Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Mattias Holm 提交于
Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Juha Riihimäki 提交于
Override access control checks (including execute) for mmu translation table descriptors assigned to manager domains. Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 07 12月, 2010 4 次提交
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由 Peter Maydell 提交于
Use the softfloat conversion routines for conversion to 16 bit integers, because just casting to a 16 bit type truncates the value rather than saturating it at 16-bit MAXINT/MININT. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NNathan Froyd <froydnj@codesourcery.com>
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由 Peter Maydell 提交于
VCVT of 16 bit fixed point to float should ignore the top 16 bits of the source register. Cast to int16_t and friends rather than int16 -- the former is guaranteed exactly 16 bits wide where the latter is merely at least 16 bits wide (and so is usually 32 bits). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NNathan Froyd <froydnj@codesourcery.com>
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由 Peter Maydell 提交于
The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NNathan Froyd <froydnj@codesourcery.com>
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由 Peter Maydell 提交于
The ARM architecture mandates that converting a NaN value to integer gives zero (if Invalid Operation FP exceptions are not being trapped). This isn't the behaviour of the SoftFloat library, so NaNs must be special-cased. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NNathan Froyd <froydnj@codesourcery.com>
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- 03 12月, 2010 2 次提交
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由 Peter Maydell 提交于
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C code as well as generated code, so we can use them to read and write the FPSCR when saving and restoring VFP registers across signal handlers in linux-user mode. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRiku Voipio <riku.voipio@nokia.com>
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由 Peter Maydell 提交于
In linux-user mode, the XScale/iWMMXT coprocessors must be enabled at reset so that we can run code that uses these instructions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 30 10月, 2010 1 次提交
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由 Stefan Weil 提交于
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: NStefan Weil <weil@mail.berlios.de> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 02 7月, 2010 1 次提交
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由 Chih-Min Chao 提交于
Signed-off-by: NChih-Min Chao <cmchao@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 01 6月, 2010 1 次提交
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由 Lars Munch 提交于
Booting an arm kernel has been broken a while when booting from non zero start address. This is due to the order of events: board init loads the kernel and sets register 15 to the start address and then qemu_system_reset reset the cpu making register 15 zero again. This patch fixes the usage of the register 15 start address trick in combination with arm_load_kernel. Signed-off-by: NLars Munch <lars@segv.dk> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 06 4月, 2010 2 次提交
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由 Paul Brook 提交于
Only include hw/loader.h from target-arm/helper.c when building for system emulation. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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由 Paul Brook 提交于
Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board reset routine to call this. Also load values directly from ROM as images have not been copied yet. Avoid clearing the NVIC pointer on cpu reset. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 27 3月, 2010 1 次提交
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由 Rabin Vincent 提交于
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection checking if the page is already in the TLB. Signed-off-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 17 3月, 2010 1 次提交
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由 Paul Brook 提交于
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 13 3月, 2010 1 次提交
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由 Paul Brook 提交于
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 19 2月, 2010 1 次提交
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由 Rabin Vincent 提交于
When handling an exception, switch to the correct mode based on the Thumb Exception (TE) bit in the SCTLR. Signed-off-by: NRabin Vincent <rabin@rab.in>
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- 07 2月, 2010 1 次提交
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由 Riku Voipio 提交于
Access the cp15.c13 TLS registers directly with TCG ops instead of with a slow helper. If the the cp15 read/write was not TLS register access, fall back to the cp15 helper. This makes accessing __thread variables in linux-user when apps are compiled with -mtp=cp15 possible. legal cp15 register to acces from linux-user are already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available only on ARMv6K and newer. Signed-off-by: NRiku Voipio <riku.voipio@nokia.com>
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- 05 2月, 2010 1 次提交
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由 Riku Voipio 提交于
Access the cp15.c13 TLS registers directly with TCG ops instead of with a slow helper. If the the cp15 read/write was not TLS register access, fall back to the cp15 helper. This makes accessing __thread variables in linux-user when apps are compiled with -mtp=cp15 possible. legal cp15 register to acces from linux-user are already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available only on ARMv6K and newer. Signed-off-by: NRiku Voipio <riku.voipio@nokia.com>
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- 23 11月, 2009 1 次提交
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由 Paul Brook 提交于
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 20 11月, 2009 2 次提交
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由 Paul Brook 提交于
Basic Cortex-A9 support. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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由 Paul Brook 提交于
Implement the ARM VFP half precision floating point extensions. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 27 10月, 2009 1 次提交
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由 Juha Riihimäki 提交于
All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 23 10月, 2009 2 次提交
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由 Aurelien Jarno 提交于
(INT32_MIN / -1) triggers an overflow, and the result depends on the host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a test to output the correct value. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com>
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由 Aurelien Jarno 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> Acked-by: NLaurent Desnogues <laurent.desnogues@gmail.com>
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