- 07 3月, 2011 3 次提交
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由 Peter Maydell 提交于
The code for Thumb2 ORNS (or negated and set flags) was trashing a TCG input register which was needed later for use in calculating flags, with the effect that the carry flag was always set with the wrong sense. Fix this by using the TCG orc op instead of separate not and or ops. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a pair of VFP single precision registers): * An incorrect condition meant these instruction patterns were being treated as load/store multiple, which resulted in the generation of bad code and a runtime segfault * The order of the core register pair was reversed so the values would go to the wrong registers Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class instruction, but in previous versions this functionality was provided via a cp15 coprocessor register. Add correct feature checks to the decoding of the cp15 WFI instructions so that they behave correctly for newer cores. In particular, the old 0,c7,c8,2 encoding used on ARM940 has been reused for VA-to-PA translation in v6 and v7. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAdam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 24 2月, 2011 3 次提交
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由 Christophe Lyon 提交于
Now use the same algorithm as described in the ARM ARM. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Now use the same algorithm as described in the ARM ARM. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
These two constants will be used by helper functions such as recpe_f32 and rsqrte_f32. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 21 2月, 2011 17 次提交
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由 Peter Maydell 提交于
For Neon shifts by immediate and narrow, correctly handle the case where the source registers and the destination registers overlap (the second pass should use the original register contents, not the results of the first pass). This includes a refactoring to pull the size check outside the loop rather than inside, since there is now very little common code between the size == 3 and size != 3 case. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Pull the code which decodes narrowing operations as being either signed/unsigned saturate or plain out into its own function. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Correctly handle VQRSHL of unsigned values by a shift count of the width of the data type or larger, which must be special-cased in the qrshl_u* helper functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Handle the case of signed VQRSHL by a shift count of the width of the data type or larger, which must be special cased in the qrshl_s* helper functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN, VQRSHRN, VQRSHRUN, taking into account whether inputs are unsigned or not. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Call the normal shift helpers instead of the rounding ones. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Fix value returned by signed 8 and 16 bit qrshl helpers when the result has saturated. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Fix range of shift amounts which always give 0 as result. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Fix handling of unsigned VRSHL.s8 and .s16 right shifts by the type width. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Correctly handle VRSHL of signed values by a shift count of the width of the data type or larger, which must be special-cased in the rshl_s* helper functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Handle cases where adding the rounding constant could overflow in Neon shift instructions: VRSHR, VRSRA, VQRSHRN, VQRSHRUN, VRSHRN. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> [peter.maydell@linaro.org: fix handling of large shifts in rshl_s32, calculate signed saturated value as other functions do.] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also give the correct answers where the inline implementation did not. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also fix the handling of the quadword version of the instruction. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Juha Riihimäki 提交于
We handle Thumb Neon data processing instructions by converting them into the equivalent ARM encoding, as the two are very close. However the ARM encoding should have bit 28 set, not clear. This wasn't causing any problems because we don't actually look at that bit during decode; however it is better to do the conversion correctly to avoid problems later if we add checks to UNDEF on SBZ/SBO bits. Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
For VQDMLSL, negation has to occur after saturation, not before. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Refactor the handling of VQDMULL so that it is dealt with in its own if() case rather than together with the accumulating instructions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply instruction). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 11 2月, 2011 5 次提交
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由 Dmitry Eremin-Solenikov 提交于
These two fields were added as a part of ARMv7 support patch (back in 2007), were never used by any code, so can be dropped. Signed-off-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com>
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由 Peter Maydell 提交于
Remove a stray #include <stdio.h> from the middle of neon_helper.c: it was harmless but pointless since we include stdio.h at the top of the file anyway. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
The Neon half-precision conversion operations (VCVT.F16.F32 and VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike the VFP versions (VCVTB and VCVTT). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Silence the NaNs that may result from half-precision conversion, as we do for the other conversions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Add a float16 type to softfloat, rather than using bits16 directly. Also add the missing functions float16_is_quiet_nan(), float16_is_signaling_nan() and float16_maybe_silence_nan(), which are needed for the float16 conversion routines. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 10 2月, 2011 4 次提交
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由 Christophe Lyon 提交于
Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Fix bit mask used when widening the result of shift on narrow input. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
The returned value when doing saturating signed 64->32 bit conversion of a negative number was incorrect due to a missing cast. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Juha Riihimäki 提交于
VQMOVUN does a signed-to-unsigned saturating conversion. This is different from both the signed-to-signed and unsigned-to-unsigned conversions already implemented, so we need a new set of helper functions (neon_unarrow_sat*). Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 05 2月, 2011 6 次提交
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由 Peter Maydell 提交于
Refine the decoding of the Thumb preload and hint space, so we UNDEF on the patterns that are supposed to UNDEF rather than NOP. We also move the tests for this space earlier, so we don't emit harmless but unnecessary address generation code for preload hints (which by their nature are likely to be in hot code paths). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Correct the decoding of the ARM preload and memory hint space, by adding decoding of PLI, PLDW and the v7MP unallocated hint space. This commit also corrects a slightly overexuberant decoding of PLD(register) which was not checking that bit 4 was one. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Peter Maydell 提交于
Add a CPU feature flag for v7MP (the multiprocessing extensions); some instructions exist only for v7MP and not for the base v7 architecture. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Christophe Lyon 提交于
This patch fixes the errors reported by my tests in VSRA. Signed-off-by: NChristophe Lyon <christophe.lyon@st.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 29 1月, 2011 1 次提交
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由 Juha Riihimäki 提交于
Correct an error in the implementation of the 16 bit forms of VQ(R)DMULH, bringing them into line with the 32 bit implementation. Signed-off-by: NJuha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 26 1月, 2011 1 次提交
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由 Peter Maydell 提交于
Fix the register and part of register we get the scalar from in the various "multiply vector by scalar" ops (VMUL by scalar and friends). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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