Add emulation of the PowerPC Decimal Floating Point Convert to
Fixed instructions dctfix[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Round to DFP Short (drsp[.]) and Round to
DFP Long (drdpq[.]) instructions.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Convert to DFP Long (dctdp[.]) and
Convert to DFP Extended (dctqpq[.]) instructions.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point (DFP) Round
to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP
Integer Without Inexact (drintn[q][.]) instructions.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Reround instructions
drrnd[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Quantize instructions
dquai[q][.] and dqua[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Test Significance
instructions dtstsf[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Test Exponent
instructions dtstex[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Test Data
Group instructions dtstdg[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Test Data Class
instructions dtstdc[q][.].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Compare instructions
dcmpu[q] and dcmpo[q].
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Divide instructions
ddiv[q][.]
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Multiply instructions
dmul[q][.]
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Subtract instructions
dsub[q][.]
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Add emulation of the PowerPC Decimal Floating Point Add instructions dadd[q][.]

Various GCC unused annotations are removed since it is now safe to remove them.
Signed-off-by: NTom Musta <tommusta@gmail.com>
[agraf: move brace in function definition]
Signed-off-by: NAlexander Graf <agraf@suse.de>

Define a floating pointer register pointer type in the PowerPC
helper header.  The type will be used to pass FPR register operands
to Decimal Floating Point (DFP) helpers.  A pointer is used because
the quad word forms of PowerPC DFP instructions operate on adjacent
pairs of floating point registers and thus can be thought of as
arrays of length 2.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

Rather than include helper.h with N values of GEN_HELPER, include a
secondary file that sets up the macros to include helper.h.  This
minimizes the files that must be rebuilt when changing the macros
for file N.
Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

This patch adds the Vector Permuate and Exclusive OR (vpermxor)
instruction introduced in Power ISA Version 2.07.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector SHA Sigma instructions introduced in Power
ISA Version 2.07:

  - Vector SHA-512 Sigma Doubleword (vshasigmad)
  - Vector SHA-256 Sigma Word (vshasigmaw)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector AES instructions introduced in Power ISA
Version 2.07:

   - Vector AES Cipher (vcipher)
   - Vector AES Cipher Last (vcipherlast)
   - Vector AES Inverse Cipher (vncipher)
   - Vector AES Inverse Cipher Last (vncipherlast)
   - Vector AES SubBytes (vsbox)

Note that the implementation of vncipher deviates from the RTL in
ISA V2.07.  However it does match the verbal description in the
third paragraph.  The RTL will be fixed in ISA V2.07B.  The
implementation here has been tested against actual P8 hardware.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch add the Binary Coded Decimal instructions bcdadd. and
bcdsub.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vectory Polynomial Multiply Sum instructions
introduced in Power ISA Version 2.07:

  - Vectory Polynomial Multiply Sum Byte (vpmsumb)
  - Vectory Polynomial Multiply Sum Halfword (vpmsumh)
  - Vectory Polynomial Multiply Sum Word (vpmsumw)
  - Vectory Polynomial Multiply Sum Doubleword (vpmsumd)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd)
instruction which is introduced in Power ISA Version 2.07.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:

  - Vector Compare Equal to Unsigned Doubleword (vcmpequd)
  - Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
  - Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)

These instructions are encoded with bit 31 set to 1 and so are duals with
vcmpeqfp, vcmpgtfp and vcmpbfp respectively.

The helper macro for integer compares is enhanced to account for 64-bit
operands.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Bit Permute Quadword (vbpermq) instruction
introduced in Power ISA Version 2.07.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Quadword Addition and Subtraction instructions
introduced in Power ISA Version 2.07:

  - Vector Add Unsigned Quadword Modulo (vadduqm)
  - Vector Add & Write Carry Unsigned Quadword (vaddcuq)
  - Vector Add Extended Unsigned Quadword (vaddeuqm)
  - Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq)
  - Vector Subtract Unsigned Quadword Modulo (vsubuqm)
  - Vector Subtract & Write Carry Unsigned Quadword (vsubcuq)
  - Vector Subtract Extended Unsigned Quadword (vsubeuqm)
  - Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:

  - Vector Rotate Left Doubleword instruction (vrld)
  - Vector Shift Left Doubleword (vsld)
  - Vector Shift Right Doubleword (vsrd)
  - Vector Shift Right Algegbraic Doubleword (vsrad)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Unpack Signed Word instructions introduced in
Power ISA Version 2.07:

  - Vector Unpack High Signed Word (vupkusw)
  - Vector Unpack Low Signed Word (vupklsw)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Pack Doubleword instructions introduced in
Power ISA Version 2.07:

 - Vector Pack Signed Doubleword Signed Saturate (vpksdss)
 - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus)
 - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum)
 - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm)
instruction.

The existing VARITH_DO macro is re-used to (trivially) instantiate
the helper code.

Since bits 21-31 of any vmuluwm instruction is 137, the instruction
is coded as a dual to vmulouw (bits 21-31 = 136).
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:

  - Vector Multiply Even Unsigned Word (vmuleuw)
  - Vector Multiply Even Signed Word (vmulesw)
  - Vector Multiply Odd Unsigned Word (vmulouw)
  - Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds two Altivec unsigned doublword modulo instructions that
are introduced in Power ISA Version V2.07:

  - vaddudm : Vector Add Unsigned Doubleword Modulo
  - vsubudm : Vector Subtrace Unsigned Doubleword Modulo
Signed-off-by: NTom Musta <tommusta@gmail.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B.  A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:

  - Floating Convert to Integer Word Unsigned (fctiwu)
  - Floating Convert to Integer Word Unsigned with Round Toward
    Zero (fctiwuz)
  - Floating Convert to Integer Doubleword Unsigned (fctidu)
  - Floating Convert to Integer Doubleword Unsigned with Round
    Toward Zero (fctiduz)

A common macro is developed to eliminate repetitious code.  Existing instructions
are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz).
Signed-off-by: NTom Musta <tommusta@gmail.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>

This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: NTom Musta <tommusta@gmail.com>
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>