- 21 9月, 2017 1 次提交
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由 Subbaraya Sundeep 提交于
Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 17 7月, 2017 4 次提交
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由 Peter Maydell 提交于
Implement a model of the Serial Communication Controller (SCC) found in MPS2 FPGA images. The primary purpose of this device is to communicate with the Motherboard Configuration Controller (MCC) which is located on the MPS board itself, outside the FPGA image. This is used for programming the MPS clock generators. The SCC also has some basic ID registers and an output for the board LEDs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement a model of the simple timer device found in the CMSDK. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Implement a model of the simple "APB UART" provided in the Cortex-M System Design Kit (CMSDK). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-3-git-send-email-peter.maydell@linaro.org Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
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由 Peter Maydell 提交于
Model the ARM MPS2/MPS2+ FPGA based development board. The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger FPGA but is otherwise the same as the 2). Since the CPU itself and most of the devices are in the FPGA, the details of the board as seen by the guest depend significantly on the FPGA image. We model the following FPGA images: "mps2_an385" -- Cortex-M3 as documented in ARM Application Note AN385 "mps2_an511" -- Cortex-M3 'DesignStart' as documented in AN511 They are fairly similar but differ in the details for some peripherals. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-2-git-send-email-peter.maydell@linaro.org Reviewed-by: NAlex Bennée <alex.bennee@linaro.org>
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- 13 6月, 2017 1 次提交
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由 Cédric Le Goater 提交于
Largely inspired by the TMP105 temperature sensor, here is a model for the TMP42{1,2,3} temperature sensors. Specs can be found here : http://www.ti.com/lit/gpn/tmp421Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
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- 24 4月, 2017 1 次提交
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由 Cédric Le Goater 提交于
The FTGMAC100 device is an Ethernet controller with DMA function that can be found on Aspeed SoCs (which include NCSI). It is fully compliant with IEEE 802.3 specification for 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 Mbps Ethernet and includes Reduced Media Independent Interface (RMII) and Reduced Gigabit Media Independent Interface (RGMII) interfaces. It adopts an AHB bus interface and integrates a link list DMA engine with direct M-Bus accesses for transmitting and receiving packets. It has independent TX/RX fifos, supports half and full duplex (1000 Mbps mode only supports full duplex), flow control for full duplex and backpressure for half duplex. The FTGMAC100 also implements IP, TCP, UDP checksum offloads and supports IEEE 802.1Q VLAN tag insertion and removal. It offers high-priority transmit queue for QoS and CoS applications This model is backed with a RealTek 8211E PHY which is the chip found on the AST2500 EVB. It is complete enough to satisfy two different Linux drivers and a U-Boot driver. Not supported features are : - IEEE 802.1Q VLAN - High Priority Transmit Queue - Wake-On-LAN functions The code is based on the Coldfire Fast Ethernet Controller model. Signed-off-by: NCédric Le Goater <clg@kaod.org> Signed-off-by: NJason Wang <jasowang@redhat.com>
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- 01 3月, 2017 1 次提交
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由 Peter Maydell 提交于
The NVIC is a core v7M device that exists for all v7M CPUs; put it under a CONFIG_ARM_V7M rather than hiding it under CONFIG_STELLARIS. (We'll use CONFIG_ARM_V7M for the SysTick device too when we split it out of the NVIC.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
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- 11 2月, 2017 1 次提交
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由 Thomas Huth 提交于
Both devices seem to be specific to the ARM platform. It's confusing for the users if they show up on other target architectures, too (e.g. when the user runs QEMU with "-device ?" to get a list of supported devices). Thus let's introduce proper configuration switches so that the devices are only compiled and included when they are really required. Signed-off-by: NThomas Huth <thuth@redhat.com> Signed-off-by: NAlex Williamson <alex.williamson@redhat.com>
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- 06 2月, 2017 1 次提交
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由 David Gibson 提交于
At present, the core device model code for 8250-like serial ports (serial.c) and the code for serial ports attached to ISA-style legacy IO (serial-isa.c) are both controlled by the CONFIG_SERIAL variable. There are lots and lots of embedded platforms that have 8250-like serial ports but have never had anything resembling ISA legacy IO. Therefore, split serial-isa into its own CONFIG_SERIAL_ISA option so it can be disabled for platforms where it's not appropriate. For now, I enabled CONFIG_SERIAL_ISA in every default-config where CONFIG_SERIAL is enabled, excepting microblaze, or32, and xtensa. As best as I can tell, those platforms never used legacy ISA, and also don't include PCI support (which would allow connection of a PCI->ISA bridge and/or a southbridge including legacy ISA serial ports). Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NThomas Huth <thuth@redhat.com> Acked-by: NChristian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com>
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- 01 2月, 2017 1 次提交
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由 Marcel Apfelbaum 提交于
The 'base' PCI Express Root Port includes the common code to be re-used for all Root Ports implementations. Most of the code was taken from the current implementation of Intel's IOH 3420 Root Port. Signed-off-by: NMarcel Apfelbaum <marcel@redhat.com> Reviewed-by: NMichael S. Tsirkin <mst@redhat.com> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 04 10月, 2016 2 次提交
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由 Alistair Francis 提交于
Add the STM32F2xx SPI device. Signed-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 14 9月, 2016 1 次提交
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由 Daniel P. Berrange 提交于
The use of the CONFIG_ISA_MMIO setting was removed in commit 61fcb628 Author: Paolo Bonzini <pbonzini@redhat.com> Date: Mon Jul 22 15:54:24 2013 +0200 isa_mmio: delete but this commit only removed it from some of the default config files. Signed-off-by: NDaniel P. Berrange <berrange@redhat.com> Message-Id: <1473096320-1638-3-git-send-email-berrange@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 04 7月, 2016 1 次提交
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由 Alistair Francis 提交于
Add a minimal model for the devcfg device which is part of Zynq. This model supports DMA capabilities and interrupt generation. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 83df49d8fa2d203a421ca71620809e4b04754e65.1467053537.git.alistair.francis@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 12 5月, 2016 1 次提交
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由 Jean-Christophe DUBOIS 提交于
For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 31 3月, 2016 1 次提交
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由 Shannon Zhao 提交于
This will be used by ARM virt machine as a power button. Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1458221140-15232-2-git-send-email-zhaoshenglong@huawei.com [PMM: Use hyphen rather than underscore in type names; add a comment briefly describing what the device does] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 17 3月, 2016 1 次提交
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由 Andrew Jeffery 提交于
Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to 8 timers can independently be configured, enabled, reset and disabled. Some hardware features are not implemented, namely clock value matching and pulse generation, but the implementation is enough to boot the Linux kernel configured with aspeed_defconfig. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-2-git-send-email-andrew@aj.id.au Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 03 2月, 2016 1 次提交
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由 Andrew Baumann 提交于
This adds the system mailboxes which are used to communicate with a number of GPU peripherals on Pi/Pi2. Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: NAndrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 9月, 2015 5 次提交
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由 Jean-Christophe Dubois 提交于
For now we support the following devices: * CPU: ARM926 * Interrupt Controller: AVIC * CCM * UART x 5 * EPIT x 2 * GPT x 4 * FEC * I2C x 3 Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
This is based on mcf_fec.c FEC implementation for Coldfire * A generic PHY was added (borrowwed from LAN9118) * The buffer management is also modified as buffers are slightly different between Coldfire and i.MX Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fb314f8a120aa49f8f6ad886f312c649b484fb5a.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
The slave mode is not implemented. Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 508dbf2ebe26ec383d3a12a1db5a7890ac8acf20.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
For now we support the following devices: * CPU: ARM1136 * Interrupt Controller: AVIC * CCM * UART x 2 * EPIT x 2 * GPT Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: f146d819594e41568daec42a1d0f440cdfe3df76.1441057361.git.jcd@tribudubois.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Wei Huang 提交于
This patch generates smbios tables for ARM mach-virt. Also add CONFIG_SMBIOS=y for ARM default config. Acked-by: NGabriel Somlo <somlo@cmu.edu> Tested-by: NGabriel Somlo <somlo@cmu.edu> Reviewed-by: NLaszlo Ersek <lersek@redhat.com> Reviewed-by: NShannon Zhao <shannon.zhao@linaro.org> Tested-by: NLeif Lindholm <leif.lindholm@linaro.org> Signed-off-by: NWei Huang <wei@redhat.com> Message-id: 1440615870-9518-3-git-send-email-wei@redhat.com [PMM: Added missing braces around an if().] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 5月, 2015 1 次提交
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由 Shannon Zhao 提交于
As core.c, piix4.c, ich9.c and pcihp.c are for x86, add CONFIG_ACPI_X86 to make it only for x86. ARM doesn't support cpu and memory hotplug, add CONFIG_ACPI_CPU_HOTPLUG and CONFIG_ACPI_MEMORY_HOTPLUG to exclude them for target-arm. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-24-git-send-email-zhaoshenglong@huawei.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 3月, 2015 1 次提交
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由 Thomas Huth 提交于
Boards that do not include an USB controller should not provide USB devices. However, when running "qemu-system-s390x -device help" for example, there's still a usb-hub, usb-kbd, usb-mouse and usb-tablet in the list of "supported" devices. Let's fix that by compiling and linking the USB files only if it is really necessary. Signed-off-by: NThomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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- 11 3月, 2015 4 次提交
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由 Alistair Francis 提交于
This patch adds the stm32f205 SoC. This will be used by the Netduino 2 to create a machine. Signed-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 48d509747a1ea0d8a7d5480560495e679990f9d2.1424175342.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This patch adds the stm32f2xx System Configuration Controller. This is used to configure what memory is mapped at address 0 (although that is not supported) as well as configure how the EXTI interrupts work (also not supported at the moment). This device is not required for basic examples, but more complex systems will require it (as well as the EXTI device) Signed-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5d499d7b60b61d5d6dcb310b2e55411b1f53794e.1424175342.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This patch adds the stm32f2xx USART controller (UART also uses the same controller). Signed-off-by: NAlistair Francis <alistair@alistair23.me> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 762c6c0d2a41d574932bc4445ec9bfffe6da8798.1424175342.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alistair Francis 提交于
This patch adds the stm32f2xx timers: TIM2, TIM3, TIM4 and TIM5 to QEMU. Signed-off-by: NAlistair Francis <alistair@alistair23.me> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 155091a323390f8da3cca496e4c611c493e62a77.1424175342.git.alistair@alistair23.me Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 27 2月, 2015 2 次提交
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由 David Gibson 提交于
Currently the "platform-bus" device is included for all softmmu builds. This bridge is intended for use on any platforms that require dynamic creation of sysbus devices. However, at present it is used only for the PPC E500 target, with plans for the ARM "virt" target in the immediate future. To avoid a not-very-useful entry appearing in "qemu -device ?" output on other targets, this patch makes a specific config option for platform-bus and enables it (for now) only on ppc configurations which include E500 and on ARM (which always includes the "virt" target). Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Message-Id: <1425017077-18487-3-git-send-email-david@gibson.dropbear.id.au> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 David Gibson 提交于
The i82801b11, ioh3420 and xio3130 PCI Express devices are currently included in the build unconditionally. While they could theoretically appear on any target platform with PCI-E, they're pretty unlikely to appear on platforms that aren't Intel derived. Therefore, to avoid presenting unlikely-to-be-relevant devices to the user, add config options to enable these components, and enable them by default only on x86 and arm platforms. (Note that this patch does include these for aarch64, via its inclusion of arm-softmmu.mak). Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-Id: <1425017077-18487-2-git-send-email-david@gibson.dropbear.id.au> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 18 2月, 2015 1 次提交
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由 David Gibson 提交于
A number of ARM embedded boards include EHCI USB host controllers which appear as directly mapped devices, rather than sitting on a PCI bus. At present code to emulate such devices is included whenever EHCI support is included. This patch adjusts teh config options to only include them in builds targetting ARM by default. Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com>
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- 13 2月, 2015 1 次提交
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由 Alexander Graf 提交于
Now that we have a working "generic" PCIe host bridge driver, we can plug it into ARM's virt machine to always have PCIe available to normal ARM VMs. I've successfully managed to expose a Bochs VGA device, XHCI and an e1000 into an AArch64 VM with this and they all lived happily ever after. Signed-off-by: NAlexander Graf <agraf@suse.de> Tested-by: NClaudio Fontana <claudio.fontana@huawei.com> [PMM: Squashed in fix for off-by-one error in bus-range DT property from Laszlo Ersek <lersek@redhat.com>] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 08 2月, 2014 1 次提交
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由 Beniamino Galvani 提交于
This patch adds support for the Fast Ethernet MAC found on Allwinner SoCs, together with a basic emulation of Realtek RTL8201CP PHY. Since there is no public documentation of the Allwinner controller, the implementation is based on Linux kernel driver. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 12月, 2013 4 次提交
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-5-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1387159292-10436-4-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 liguang 提交于
Signed-off-by: Nliguang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387159292-10436-3-git-send-email-lig.fnst@cn.fujitsu.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Antony Pavlov 提交于
DIGIC is Canon Inc.'s name for a family of SoC for digital cameras and camcorders. There is no publicly available specification for DIGIC chips. All information about DIGIC chip internals is based on reverse engineering efforts made by CHDK (http://chdk.wikia.com) and Magic Lantern (http://www.magiclantern.fm) projects contributors. Signed-off-by: NAntony Pavlov <antonynpavlov@gmail.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1387188908-754-2-git-send-email-antonynpavlov@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 12月, 2013 1 次提交
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由 Peter Crosthwaite 提交于
The ARM A9 MPCore has a timer that is global to all cores in the cluster. The timer is shared but each core has a private independent comparator and interrupt. Based on version contributed by Francois LEGAL. Signed-off-by: NFrançois LEGAL <devel@thom.fr.eu.org> Message-id: 4918e89476b8da916be2964ec41578b50d569a37.1385969450.git.peter.crosthwaite@xilinx.com [PC changes: * New commit message * Re-implemented as single timer model * Fixed backwards counting issue in polled mode * completed VMSD fields * macroified magic numbers (and headerified reg definitions) * split of as device-model-only patch * use bitops for 64 bit register access * Fixed auto increment mode to check condition properly * general cleanup (names/style etc). ] Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> [PMM: * minor typo fixes * added missing return after error_setg() * dropped setting dc->no_user = 1 ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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