- 21 9月, 2017 40 次提交
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由 Subbaraya Sundeep 提交于
Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Modelled Microsemi's Smartfusion2 SPI controller. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-4-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Acked-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-3-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Subbaraya Sundeep 提交于
Modelled System Timer in Microsemi's Smartfusion2 Soc. Timer has two 32bit down counters and two interrupts. Signed-off-by: NSubbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Acked-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-2-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Don't use old_mmio in the memory region ops struct. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Don't use old_mmio in the memory region ops struct. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Don't use the old_mmio struct in memory region ops. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Don't use the old_mmio in the memory region ops struct. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Drop the use of old_mmio in the omap2_gpio memory ops. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update the static_ops functions to use new-style mmio rather than the legacy old_mmio functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505580378-9044-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In the A64 decoder, we have a lot of references to section numbers from version A.a of the v8A ARM ARM (DDI0487). This version of the document is now long obsolete (we are currently on revision B.a), and various intervening versions renumbered all the sections. The most recent B.a version of the document doesn't assign section numbers at all to the individual instruction classes in the way that the various A.x versions did. The simplest thing to do is just to delete all the out of date C.x.x references. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 20170915150849.23557-1-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq() to handle banked exceptions: * acknowledge needs to use the correct vector, which may be in sec_vectors[] * acknowledge needs to return to its caller whether the exception should be taken to secure or non-secure state * complete needs its caller to tell it whether the exception being completed is a secure one or not Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-20-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Handle banking of SHCSR: some register bits are banked between Secure and Non-Secure, and some are only accessible to Secure. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-19-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The ICSR NVIC register is banked for v8M. This doesn't require any new state, but it does mean that some bits are controlled by BFHNFNMINS and some bits must work with the correct banked exception. There is also a new in v8M PENDNMICLR bit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-18-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Now that we have a banked FAULTMASK register and banked exceptions, we can implement the correct check in cpu_mmu_index() for whether the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes handlers which have requested a negative execution priority to run with the MPU disabled. In v8M the test has to check this for the current security state and so takes account of banking. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-17-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update nvic_exec_prio() to support the v8M changes: * BASEPRI, FAULTMASK and PRIMASK are all banked * AIRCR.PRIS can affect NS priorities * AIRCR.BFHFNMINS affects FAULTMASK behaviour These changes mean that it's no longer possible to definitely say that if FAULTMASK is set it overrides PRIMASK, and if PRIMASK is set it overrides BASEPRI (since if PRIMASK_NS is set and AIRCR.PRIS is set then whether that 0x80 priority should take effect or the priority in BASEPRI_S depends on the value of BASEPRI_S, for instance). So we switch to the same approach used by the pseudocode of working through BASEPRI, PRIMASK and FAULTMASK and overriding the previous values if needed. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-16-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually preempt execution. The simple way to achieve this is to clear the enable bit for it, since the enable bit isn't guest visible. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In v7M, the fixed-priority exceptions are: Reset: -3 NMI: -2 HardFault: -1 In v8M, this changes because Secure HardFault may need to be prioritised above NMI: Reset: -4 Secure HardFault if AIRCR.BFHFNMINS == 1: -3 NMI: -2 Secure HardFault if AIRCR.BFHFNMINS == 0: -1 NonSecure HardFault: -1 Make these changes, including support for changing the priority of Secure HardFault as AIRCR.BFHFNMINS changes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-14-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
When escalating to HardFault, we must go into Lockup if we can't take the synchronous HardFault because the current execution priority is already at or below the priority of HardFault. In v7M HF is always priority -1 so a simple < 0 comparison sufficed; in v8M the priority of HardFault can vary depending on whether it is a Secure or NonSecure HardFault, so we must check against the priority of the HardFault exception vector we're about to use. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-13-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
In armv7m_nvic_set_pending() we have to compare the priority of an exception against the execution priority to decide whether it needs to be escalated to HardFault. In the specification this is a comparison against the exception's group priority; for v7M we implemented it as a comparison against the raw exception priority because the two comparisons will always give the same answer. For v8M the existence of AIRCR.PRIS and the possibility of different PRIGROUP values for secure and nonsecure exceptions means we need to explicitly calculate the vector's group priority for this check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-12-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Make the set_prio() function take a bool indicating whether to pend the secure or non-secure version of a banked interrupt, and use this to implement the correct banking semantics for the SHPR registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-11-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending() functions take a bool indicating whether to pend the secure or non-secure version of a banked interrupt, and update the callsites accordingly. In most callsites we can simply pass the correct security state in; in a couple of cases we use TODO comments to indicate that we will return the code in a subsequent commit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-10-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update the nvic_recompute_state() code to handle the security extension and its associated banked registers. Code that uses the resulting cached state (ie the irq acknowledge and complete code) will be updated in a later commit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
For v8M, the NVIC has a new set of registers per interrupt, NVIC_ITNS<n>. These determine whether the interrupt targets Secure or Non-secure state. Implement the register read/write code for these, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER, NVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure accesses to fields corresponding to interrupts which are configured to target secure state. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-8-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Update the code in nvic_rettobase() so that it checks the sec_vectors[] array as well as the vectors[] array if needed. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-7-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The Application Interrupt and Reset Control Register has some changes for v8M: * new bits SYSRESETREQS, BFHFNMINS and PRIS: these all have real state if the security extension is implemented and otherwise are constant * the PRIGROUP field is banked between security states * non-secure code can be blocked from using the SYSRESET bit to reset the system if SYSRESETREQS is set Implement the new state and the changes to register read and write. For the moment we ignore the effects of the secure PRIGROUP. We will implement the effects of PRIS and BFHFNMIS later. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Instead of looking up the pending priority in nvic_pending_prio(), cache it in a new state struct field. The calculation of the pending priority given the interrupt number is more complicated in v8M with the security extension, so the caching will be worthwhile. This changes nvic_pending_prio() from returning a full (group + subpriority) priority value to returning a group priority. This doesn't require changes to its callsites because we use it only in comparisons of the form execution_prio > nvic_pending_prio() and execution priority is always a group priority, so a test (exec prio > full prio) is true if and only if (execprio > group_prio). (Architecturally the expected comparison is with the group priority for this sort of "would we preempt" test; we were only doing a test with a full priority as an optimisation to avoid the mask, which is possible precisely because the two comparisons always give the same answer.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
With banked exceptions, just the exception number in s->vectpending is no longer sufficient to uniquely identify the pending exception. Add a vectpending_is_s_banked bool which is true if the exception is using the sec_vectors[] array. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1505240046-11454-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
For the v8M security extension, some exceptions must be banked between security states. Add the new vecinfo array which holds the state for the banked exceptions and migrate it if the CPU the NVIC is attached to implements the security extension. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
In v8M the MSR and MRS instructions have extra register value encodings to allow secure code to access the non-secure banked version of various special registers. (We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because we don't currently implement the stack limit registers at all.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-id: 1505240046-11454-2-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
MIPS patches 2017-09-21 Changes: QOMify MIPS cpu Improve macro parenthesization # gpg: Signature made Thu 21 Sep 2017 13:50:37 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170921: mips: Improve macro parenthesization mips: replace cpu_mips_init() with cpu_generic_init() mips: MIPSCPU model subclasses mips: call cpu_mips_realize_env() from mips_cpu_realizefn() mips: split cpu_mips_realize_env() out of cpu_mips_init() mips: introduce internal.h and cleanup cpu.h mips: move hw/mips/cputimer.c to target/mips/ Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Eric Blake 提交于
Although none of the existing macro call-sites were broken, it's always better to write macros that properly parenthesize arguments that can be complex expressions, so that the intended order of operations is not broken. Signed-off-by: NEric Blake <eblake@redhat.com> Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Igor Mammedov 提交于
now cpu_mips_init() reimplements subset of cpu_generic_init() tasks, so just drop it and use cpu_generic_init() directly. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NHervé Poussineau <hpoussin@reactos.org> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> [PMD: use internal.h instead of cpu.h] Tested-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Igor Mammedov 提交于
Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: NIgor Mammedov <imammedo@redhat.com> Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> [PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass, mark MIPSCPU abstract, address Eduardo Habkost review] Tested-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Philippe Mathieu-Daudé 提交于
This changes the order between cpu_mips_realize_env() and cpu_exec_initfn(), but cpu_exec_initfn() don't have anything that depends on cpu_mips_realize_env() being called first. Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NIgor Mammedov <imammedo@redhat.com> Tested-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Philippe Mathieu-Daudé 提交于
so it can be used in mips_cpu_realizefn() in the next commit Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NIgor Mammedov <imammedo@redhat.com> Tested-by: NJames Hogan <james.hogan@imgtec.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Philippe Mathieu-Daudé 提交于
no logical change, only code movement (and fix a comment typo). Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NIgor Mammedov <imammedo@redhat.com> Tested-by: NJames Hogan <james.hogan@imgtec.com> Acked-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Philippe Mathieu-Daudé 提交于
This timer is a required part of the MIPS32/MIPS64 System Control coprocessor (CP0). Moving it with the other architecture related files will allow an opaque use of CPUMIPSState* in the next commit (introduce "internal.h"). also remove it from 'user' targets, remove an unnecessary include. Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NIgor Mammedov <imammedo@redhat.com> Tested-by: NJames Hogan <james.hogan@imgtec.com> Acked-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NYongbok Kim <yongbok.kim@imgtec.com>
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由 Peter Maydell 提交于
qemu-sparc update # gpg: Signature made Thu 21 Sep 2017 08:42:30 BST # gpg: using RSA key 0x5BC2C56FAE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-signed: sun4u: use sunhme as default on-board NIC net: add Sun HME (Happy Meal Ethernet) on-board NIC Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Xen 2017/09/20 # gpg: Signature made Thu 21 Sep 2017 03:20:02 BST # gpg: using RSA key 0x894F8F4870E1AE90 # gpg: Good signature from "Stefano Stabellini <stefano.stabellini@eu.citrix.com>" # gpg: aka "Stefano Stabellini <sstabellini@kernel.org>" # Primary key fingerprint: D04E 33AB A51F 67BA 07D3 0AEA 894F 8F48 70E1 AE90 * remotes/sstabellini/tags/xen-20170920-tag: xen/pt: allow QEMU to request MSI unmasking at bind time xen-disk: use g_new0 to fix build Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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