- 23 9月, 2016 2 次提交
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由 Cédric Le Goater 提交于
Based on previous work done by Andrew Jeffery <andrew@aj.id.au>. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-9-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Cédric Le Goater 提交于
This gives some explanation behind the magic number 0x120CE416. Signed-off-by: NCédric Le Goater <clg@kaod.org> Reviewed-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-8-git-send-email-clg@kaod.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 14 7月, 2016 1 次提交
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由 Cédric Le Goater 提交于
AST2400_A0_SILICON_REV is defined twice. Fix this by including the definition in the header file as well as the routine to check if a silicon revision is supported. It will useful to reuse in other controllers. Let's add also AST2500_A0_SILICON_REV for future use. Signed-off-by: NCédric Le Goater <clg@kaod.org> Message-id: 1467994016-11678-5-git-send-email-clg@kaod.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 27 6月, 2016 1 次提交
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由 Andrew Jeffery 提交于
The SCU is a collection of chip-level control registers that manage the various functions supported by ASPEED SoCs. Typically the bits control interactions with clocks, external hardware or reset behaviour, and we can largly take a hands-off approach to reads and writes. Firmware makes heavy use of the state to determine how to boot, but the reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev property is exposed so that the integrating SoC model can configure the silicon revision, which in-turn selects the appropriate reset values. Further qdev properties are exposed so the board model can configure the board-dependent hardware strapping. Almost all provided AST2400 reset values are specified by the datasheet. The notable exception is SOC_SCRATCH1, where we mark the DRAM as successfully initialised to avoid unnecessary dark corners in the SoC's u-boot support. Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Message-id: 1466744305-23163-2-git-send-email-andrew@aj.id.au Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> [PMM: drop unnecessary inttypes.h include] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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