- 06 10月, 2011 28 次提交
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由 Alexander Graf 提交于
We currently load a device tree blob and then just take its size x2 to account for modifications we do inside. While this is nice and great, it fails when we have a small device tree as blob and lots of nodes added in machine init code. So for now, just make it 20k bigger than it was before. We maybe want to be more clever about this later. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
When we screw up and issue an FDT command that doesn't work, we really need to know immediately and usually can't continue to create the machine. To make sure we don't need to add error checking in all device tree modification code users, we can just add the fail checks to the qemu abstract functions. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We want to be able to create subnodes in our device tree, so export it through the qemu device tree abstraction framework. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The guest OS wants to know where the guest spins, so let's tell him while updating the CPU nodes with the frequencies anyways. Signed-off-by: NAlexander Graf <agraf@suse.de> --- v1 -> v2: - use new spin table address
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由 Alexander Graf 提交于
CPUs that are not the boot CPU need to run in spinning code to check if they should run off to execute and if so where to jump to. This usually happens by leaving secondary CPUs looping and checking if some variable in memory changed. In an environment like Qemu however we can be more clever. We can just export the spin table the primary CPU modifies as MMIO region that would event based wake up the respective secondary CPUs. That saves us quite some cycles while the secondary CPUs are not up yet. So this patch adds a PV device that simply exports the spinning table into the guest and thus allows the primary CPU to wake up secondary ones. Signed-off-by: NAlexander Graf <agraf@suse.de> --- v1 -> v2: - change into MMIO scheme - map the secondary NIP instead of 0 1:1 - only map 64MB for TLB, same as u-boot - prepare code for 64-bit spinnings v2 -> v3: - remove r6 - set MAS2_M - map EA 0 - use second TLB1 entry v3 -> v4: - change to memoryops v4 -> v5: - fix endianness bugs v5 -> v6: - add header
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由 Alexander Graf 提交于
We should only keep CPU nodes in the device tree around that we really have virtual CPUs for. So remove all superfluous entries that we just keep there in case someone wants to create a lot of vCPUs. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Now that we can so nicely find out the host's frequencies, we should also make sure that we get them into all virtual CPUs' device tree nodes. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We have a bunch of helper functions that don't have any stubs for them in case we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can optimize them out pretty well, but we should really provide them. Signed-off-by: NAlexander Graf <agraf@suse.de> --- v1 -> v2: - use uint64_t for clockfreq
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由 Alexander Graf 提交于
We just got rid of the last user of kvmppc_read_host_property, so we can now safely remove it. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Now that we have nice and shiny APIs to read out the host's clock and timebase frequencies, let's use them in the bamboo code as well! Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading host values and writing guest values respectively. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Now that we have generic KVM functions to read out the host tb and clock frequencies, let's use them in the e500 code! Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We need to find out the host's clock-frequency when running on KVM, so let's export a respective function. Signed-off-by: NAlexander Graf <agraf@suse.de> --- v1 -> v2: - enable 64bit values
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由 Alexander Graf 提交于
We have some code in generic kvm_ppc.c that is only used by 440. Move to the 440 specific device code. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We have a qemu internal abstraction layer on FDT. While I'm not fully convinced we need it at all, it's missing the nop_node functionality that we now need on e500. So let's add it and think about the general future of that API later. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Now that we can generate multiple envs for all our virtual CPUs, we also need to tell the MPIC that we have multiple CPUs connected and connect them all to the respective virtual interrupt lines. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
When creating a VM, we should go through smp_cpus and create a virtual CPU for every CPU the user requested. This patch adds support for that and moves some code around to make that more convenient. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: NAlexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 due to cINT routing - Report nb_cpus not MAX_CPUS in MPIC capabilities
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由 Alexander Graf 提交于
The bit definitions for critical interrupt routing are in PowerPC order (most significant bit is 0), while we end up shifting it with normal bit order. Turn the numbers around so we actually end up fetching the right ones. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The IPI dispatch registers are write only according to every MPIC spec I have found. So instead of pretending you could read back something from them, better not handle them at all. Reported-by: NElie Richa <richa@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We use the IDE register with IPIs as a mask to keep track which processors have already acknowledged the respective interrupt. So we need to initialize it to 0 to make sure that it doesn't accidently fire an IPI on CPU0 when the first IPI is triggered. Reported-by: NElie Richa <richa@adacore.com> Signed-off-by: NAlexander Graf <agraf@suse.de> --- v2 -> v3: - fix IDE IPI reset
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由 Alexander Graf 提交于
The current IPI support in the MPIC code is incomplete and doesn't work. This code adds proper support for IPIs in MPIC by using the IDE register to remember which CPUs IPIs are still outstanding to. New triggers through the IPI trigger register only add to the list of CPUs we want to IPI. Signed-off-by: NAlexander Graf <agraf@suse.de> --- v1 -> v2: - Use MAX_IPI instead of hardcoded 4 Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The MPIC exports a page for each CPU that it controls. To support more than one CPU, we need to also reserve the MMIO space according to the amount of CPUs we want to support. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The MPIC exports a register set for each CPU connected to it. They can all be accessed through specific registers or using a shadow page that is mapped differently depending on which CPU accesses it. This patch implements the shadow map, making it possible for guests to access the CPU local registers using the same address on each CPU. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The MPIC has some funny feature where it maps different registers to an MMIO region depending which CPU accesses them. To be able to reflect that, we need to make OpenPIC be compiled in the target code, so it can access cpu_single_env. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Paolo Bonzini 提交于
This also lets the user see the irq in "info qtree". Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Paolo Bonzini 提交于
Restructure common properties for sPAPR devices so that IRQ definitions can be added in one place. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Paolo Bonzini 提交于
Right now the spapr devices cannot be instantiated with -device, because the IRQs need to be passed to the spapr_*_create functions. Do this instead in the bus's init wrapper. This is particularly important with the conversion from scsi-disk to scsi-{cd,hd} that Markus made. After his patches, if you specify a scsi-cd device attached to an if=none drive, the default VSCSI controller will not be created and, without qdevification, you will not be able to add yours. NOTE from agraf: added small compile fix Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 05 10月, 2011 1 次提交
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由 Stefan Hajnoczi 提交于
QED's metadata caching strategy allows two parallel requests to race for metadata lookup. The first one to complete will populate the metadata cache and the second one will drop the data it just read in favor of the cached data. There is a use-after-free in qed_read_l2_table_cb() and qed_commit_l2_update() where l2_table->offset was used after the l2_table may have been freed due to a metadata lookup race. Fix this by keeping the l2_offset in a local variable and not reaching into the possibly freed l2_table. Reported-by: NAmit Shah <amit.shah@redhat.com> Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 03 10月, 2011 1 次提交
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由 Edgar E. Iglesias 提交于
Reported-by: NStefan Weil <weil@mail.berlios.de> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@gmail.com>
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- 02 10月, 2011 4 次提交
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由 Jan Kiszka 提交于
Makes reading the output more user friendly. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NAvi Kivity <avi@redhat.com>
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由 Jan Kiszka 提交于
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NAvi Kivity <avi@redhat.com>
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由 Jan Kiszka 提交于
Useful to discover eclipses. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NAvi Kivity <avi@redhat.com>
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由 Blue Swirl 提交于
Add a monitor command 'info mtree' to show the memory hierarchy much like /proc/iomem in Linux. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAvi Kivity <avi@redhat.com>
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- 01 10月, 2011 6 次提交
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由 Blue Swirl 提交于
GETPC() can be used even from outside of helper code. Move the macro to a more accessible location. Avoid a compile warning from redefining it in exec.c. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Add some comments to describe each file. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Alexander Graf 提交于
We are mapping ESCC to a static (incorrect) address on machine init. This overlaps with our vram, rendering the screen barely usable. Since openBIOS is clever enough to map ESCC to where it needs to be, we can just drop that invalid map and everyone's happy. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Jan Kiszka 提交于
x86 cannot provide an optimized generic deposit implementation. But at least for a few special cases, namely for writing bits 0..7, 8..15, and 0..15, versions using only a single instruction are feasible. Introducing such limited support improves emulating 16-bit x86 code on x86, but also rarer cases where 32-bit or 64-bit code accesses bytes or words. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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