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体验新版 GitCode,发现更多精彩内容 >>
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bf4b9889
编写于
9月 11, 2011
作者:
B
Blue Swirl
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
ESP: convert to trace framework
Signed-off-by:
N
Blue Swirl
<
blauwirbel@gmail.com
>
上级
b39491a8
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
61 addition
and
40 deletion
+61
-40
hw/esp.c
hw/esp.c
+30
-40
trace-events
trace-events
+31
-0
未找到文件。
hw/esp.c
浏览文件 @
bf4b9889
...
...
@@ -25,9 +25,7 @@
#include "sysbus.h"
#include "scsi.h"
#include "esp.h"
/* debug ESP card */
//#define DEBUG_ESP
#include "trace.h"
/*
* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
...
...
@@ -37,13 +35,6 @@
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
*/
#ifdef DEBUG_ESP
#define DPRINTF(fmt, ...) \
do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...) do {} while (0)
#endif
#define ESP_ERROR(fmt, ...) \
do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
...
...
@@ -158,7 +149,7 @@ static void esp_raise_irq(ESPState *s)
if
(
!
(
s
->
rregs
[
ESP_RSTAT
]
&
STAT_INT
))
{
s
->
rregs
[
ESP_RSTAT
]
|=
STAT_INT
;
qemu_irq_raise
(
s
->
irq
);
DPRINTF
(
"Raise IRQ
\n
"
);
trace_esp_raise_irq
(
);
}
}
...
...
@@ -167,7 +158,7 @@ static void esp_lower_irq(ESPState *s)
if
(
s
->
rregs
[
ESP_RSTAT
]
&
STAT_INT
)
{
s
->
rregs
[
ESP_RSTAT
]
&=
~
STAT_INT
;
qemu_irq_lower
(
s
->
irq
);
DPRINTF
(
"Lower IRQ
\n
"
);
trace_esp_lower_irq
(
);
}
}
...
...
@@ -178,13 +169,13 @@ static void esp_dma_enable(void *opaque, int irq, int level)
if
(
level
)
{
s
->
dma_enabled
=
1
;
DPRINTF
(
"Raise enable
\n
"
);
trace_esp_dma_enable
(
);
if
(
s
->
dma_cb
)
{
s
->
dma_cb
(
s
);
s
->
dma_cb
=
NULL
;
}
}
else
{
DPRINTF
(
"Lower enable
\n
"
);
trace_esp_dma_disable
(
);
s
->
dma_enabled
=
0
;
}
}
...
...
@@ -214,7 +205,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf)
memcpy
(
buf
,
s
->
ti_buf
,
dmalen
);
buf
[
0
]
=
buf
[
2
]
>>
5
;
}
DPRINTF
(
"get_cmd: len %d target %d
\n
"
,
dmalen
,
target
);
trace_esp_get_cmd
(
dmalen
,
target
);
s
->
ti_size
=
0
;
s
->
ti_rptr
=
0
;
...
...
@@ -243,7 +234,7 @@ static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
int32_t
datalen
;
int
lun
;
DPRINTF
(
"do_busid_cmd: busid 0x%x
\n
"
,
busid
);
trace_esp_do_busid_cmd
(
busid
);
lun
=
busid
&
7
;
s
->
current_req
=
scsi_req_new
(
s
->
current_dev
,
0
,
lun
,
buf
,
NULL
);
datalen
=
scsi_req_enqueue
(
s
->
current_req
);
...
...
@@ -308,7 +299,7 @@ static void handle_satn_stop(ESPState *s)
}
s
->
cmdlen
=
get_cmd
(
s
,
s
->
cmdbuf
);
if
(
s
->
cmdlen
)
{
DPRINTF
(
"Set ATN & Stop: cmdlen %d
\n
"
,
s
->
cmdlen
);
trace_esp_handle_satn_stop
(
s
->
cmdlen
);
s
->
do_cmd
=
1
;
s
->
rregs
[
ESP_RSTAT
]
=
STAT_TC
|
STAT_CD
;
s
->
rregs
[
ESP_RINTR
]
=
INTR_BS
|
INTR_FC
;
...
...
@@ -319,7 +310,7 @@ static void handle_satn_stop(ESPState *s)
static
void
write_response
(
ESPState
*
s
)
{
DPRINTF
(
"Transfer status (status=%d)
\n
"
,
s
->
status
);
trace_esp_write_response
(
s
->
status
);
s
->
ti_buf
[
0
]
=
s
->
status
;
s
->
ti_buf
[
1
]
=
0
;
if
(
s
->
dma
)
{
...
...
@@ -355,7 +346,7 @@ static void esp_do_dma(ESPState *s)
to_device
=
(
s
->
ti_size
<
0
);
len
=
s
->
dma_left
;
if
(
s
->
do_cmd
)
{
DPRINTF
(
"command len %d + %d
\n
"
,
s
->
cmdlen
,
len
);
trace_esp_do_dma
(
s
->
cmdlen
,
len
);
s
->
dma_memory_read
(
s
->
dma_opaque
,
&
s
->
cmdbuf
[
s
->
cmdlen
],
len
);
s
->
ti_size
=
0
;
s
->
cmdlen
=
0
;
...
...
@@ -400,15 +391,15 @@ static void esp_command_complete(SCSIRequest *req, uint32_t status)
{
ESPState
*
s
=
DO_UPCAST
(
ESPState
,
busdev
.
qdev
,
req
->
bus
->
qbus
.
parent
);
DPRINTF
(
"SCSI Command complete
\n
"
);
trace_esp_command_complete
(
);
if
(
s
->
ti_size
!=
0
)
{
DPRINTF
(
"SCSI command completed unexpectedly
\n
"
);
trace_esp_command_complete_unexpected
(
);
}
s
->
ti_size
=
0
;
s
->
dma_left
=
0
;
s
->
async_len
=
0
;
if
(
status
)
{
DPRINTF
(
"Command failed
\n
"
);
trace_esp_command_complete_fail
(
);
}
s
->
status
=
status
;
s
->
rregs
[
ESP_RSTAT
]
=
STAT_ST
;
...
...
@@ -424,7 +415,7 @@ static void esp_transfer_data(SCSIRequest *req, uint32_t len)
{
ESPState
*
s
=
DO_UPCAST
(
ESPState
,
busdev
.
qdev
,
req
->
bus
->
qbus
.
parent
);
DPRINTF
(
"transfer %d/%d
\n
"
,
s
->
dma_left
,
s
->
ti_size
);
trace_esp_transfer_data
(
s
->
dma_left
,
s
->
ti_size
);
s
->
async_len
=
len
;
s
->
async_buf
=
scsi_req_get_buf
(
req
);
if
(
s
->
dma_left
)
{
...
...
@@ -452,13 +443,13 @@ static void handle_ti(ESPState *s)
minlen
=
(
dmalen
<
-
s
->
ti_size
)
?
dmalen
:
-
s
->
ti_size
;
else
minlen
=
(
dmalen
<
s
->
ti_size
)
?
dmalen
:
s
->
ti_size
;
DPRINTF
(
"Transfer Information len %d
\n
"
,
minlen
);
trace_esp_handle_ti
(
minlen
);
if
(
s
->
dma
)
{
s
->
dma_left
=
minlen
;
s
->
rregs
[
ESP_RSTAT
]
&=
~
STAT_TC
;
esp_do_dma
(
s
);
}
else
if
(
s
->
do_cmd
)
{
DPRINTF
(
"command len %d
\n
"
,
s
->
cmdlen
);
trace_esp_handle_ti_cmd
(
s
->
cmdlen
);
s
->
ti_size
=
0
;
s
->
cmdlen
=
0
;
s
->
do_cmd
=
0
;
...
...
@@ -517,7 +508,7 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
uint32_t
saddr
,
old_val
;
saddr
=
addr
>>
s
->
it_shift
;
DPRINTF
(
"read reg[%d]: 0x%2.2x
\n
"
,
saddr
,
s
->
rregs
[
saddr
]);
trace_esp_mem_readb
(
saddr
,
s
->
rregs
[
saddr
]);
switch
(
saddr
)
{
case
ESP_FIFO
:
if
(
s
->
ti_size
>
0
)
{
...
...
@@ -558,8 +549,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
uint32_t
saddr
;
saddr
=
addr
>>
s
->
it_shift
;
DPRINTF
(
"write reg[%d]: 0x%2.2x -> 0x%2.2x
\n
"
,
saddr
,
s
->
wregs
[
saddr
],
val
);
trace_esp_mem_writeb
(
saddr
,
s
->
wregs
[
saddr
],
val
);
switch
(
saddr
)
{
case
ESP_TCLO
:
case
ESP_TCMID
:
...
...
@@ -587,21 +577,21 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
}
switch
(
val
&
CMD_CMD
)
{
case
CMD_NOP
:
DPRINTF
(
"NOP (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_nop
(
val
);
break
;
case
CMD_FLUSH
:
DPRINTF
(
"Flush FIFO (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_flush
(
val
);
//s->ti_size = 0;
s
->
rregs
[
ESP_RINTR
]
=
INTR_FC
;
s
->
rregs
[
ESP_RSEQ
]
=
0
;
s
->
rregs
[
ESP_RFLAGS
]
=
0
;
break
;
case
CMD_RESET
:
DPRINTF
(
"Chip reset (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_reset
(
val
);
esp_soft_reset
(
&
s
->
busdev
.
qdev
);
break
;
case
CMD_BUSRESET
:
DPRINTF
(
"Bus reset (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_bus_reset
(
val
);
s
->
rregs
[
ESP_RINTR
]
=
INTR_RST
;
if
(
!
(
s
->
wregs
[
ESP_CFG1
]
&
CFG1_RESREPT
))
{
esp_raise_irq
(
s
);
...
...
@@ -611,41 +601,41 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
handle_ti
(
s
);
break
;
case
CMD_ICCS
:
DPRINTF
(
"Initiator Command Complete Sequence (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_iccs
(
val
);
write_response
(
s
);
s
->
rregs
[
ESP_RINTR
]
=
INTR_FC
;
s
->
rregs
[
ESP_RSTAT
]
|=
STAT_MI
;
break
;
case
CMD_MSGACC
:
DPRINTF
(
"Message Accepted (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_msgacc
(
val
);
s
->
rregs
[
ESP_RINTR
]
=
INTR_DC
;
s
->
rregs
[
ESP_RSEQ
]
=
0
;
s
->
rregs
[
ESP_RFLAGS
]
=
0
;
esp_raise_irq
(
s
);
break
;
case
CMD_PAD
:
DPRINTF
(
"Transfer padding (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_pad
(
val
);
s
->
rregs
[
ESP_RSTAT
]
=
STAT_TC
;
s
->
rregs
[
ESP_RINTR
]
=
INTR_FC
;
s
->
rregs
[
ESP_RSEQ
]
=
0
;
break
;
case
CMD_SATN
:
DPRINTF
(
"Set ATN (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_satn
(
val
);
break
;
case
CMD_SEL
:
DPRINTF
(
"Select without ATN (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_sel
(
val
);
handle_s_without_atn
(
s
);
break
;
case
CMD_SELATN
:
DPRINTF
(
"Select with ATN (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_selatn
(
val
);
handle_satn
(
s
);
break
;
case
CMD_SELATNS
:
DPRINTF
(
"Select with ATN & stop (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_selatns
(
val
);
handle_satn_stop
(
s
);
break
;
case
CMD_ENSEL
:
DPRINTF
(
"Enable selection (%2.2x)
\n
"
,
val
);
trace_esp_mem_writeb_cmd_ensel
(
val
);
s
->
rregs
[
ESP_RINTR
]
=
0
;
break
;
default:
...
...
trace-events
浏览文件 @
bf4b9889
...
...
@@ -502,3 +502,34 @@ escc_sunkbd_event_in(int ch) "Untranslated keycode %2.2x"
escc_sunkbd_event_out(int ch) "Translated keycode %2.2x"
escc_kbd_command(int val) "Command %d"
escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x"
# hw/esp.c
esp_raise_irq(void) "Raise IRQ"
esp_lower_irq(void) "Lower IRQ"
esp_dma_enable(void) "Raise enable"
esp_dma_disable(void) "Lower enable"
esp_get_cmd(uint32_t dmalen, int target) "len %d target %d"
esp_do_busid_cmd(uint8_t busid) "busid 0x%x"
esp_handle_satn_stop(uint32_t cmdlen) "cmdlen %d"
esp_write_response(uint32_t status) "Transfer status (status=%d)"
esp_do_dma(uint32_t cmdlen, uint32_t len) "command len %d + %d"
esp_command_complete(void) "SCSI Command complete"
esp_command_complete_unexpected(void) "SCSI command completed unexpectedly"
esp_command_complete_fail(void) "Command failed"
esp_transfer_data(uint32_t dma_left, int32_t ti_size) "transfer %d/%d"
esp_handle_ti(uint32_t minlen) "Transfer Information len %d"
esp_handle_ti_cmd(uint32_t cmdlen) "command len %d"
esp_mem_readb(uint32_t saddr, uint8_t reg) "reg[%d]: 0x%2.2x"
esp_mem_writeb(uint32_t saddr, uint8_t reg, uint32_t val) "reg[%d]: 0x%2.2x -> 0x%2.2x"
esp_mem_writeb_cmd_nop(uint32_t val) "NOP (%2.2x)"
esp_mem_writeb_cmd_flush(uint32_t val) "Flush FIFO (%2.2x)"
esp_mem_writeb_cmd_reset(uint32_t val) "Chip reset (%2.2x)"
esp_mem_writeb_cmd_bus_reset(uint32_t val) "Bus reset (%2.2x)"
esp_mem_writeb_cmd_iccs(uint32_t val) "Initiator Command Complete Sequence (%2.2x)"
esp_mem_writeb_cmd_msgacc(uint32_t val) "Message Accepted (%2.2x)"
esp_mem_writeb_cmd_pad(uint32_t val) "Transfer padding (%2.2x)"
esp_mem_writeb_cmd_satn(uint32_t val) "Set ATN (%2.2x)"
esp_mem_writeb_cmd_sel(uint32_t val) "Select without ATN (%2.2x)"
esp_mem_writeb_cmd_selatn(uint32_t val) "Select with ATN (%2.2x)"
esp_mem_writeb_cmd_selatns(uint32_t val) "Select with ATN & stop (%2.2x)"
esp_mem_writeb_cmd_ensel(uint32_t val) "Enable selection (%2.2x)"
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