Support JPS1 little endian block transfer ASIs.
Signed-off-by: NTsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Support UA2007 block store ASIs for stfa instructions.
Signed-off-by: NTsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Support UA2007 block load ASIs for ldfa instructions.
Signed-off-by: NTsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.
Signed-off-by: NTsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

This patch implements sparcv9 ldfa/lddfa/ldqfa instructions
with non block-load ASIs.
Signed-off-by: NTsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

do_interrupt() was mixing CPUState pointer passed from caller
and global env (AREG0).

Fix by moving the function to helper.c. Introduce a helper for calling
change_pstate() safely from outside of execution context.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Before the next patch, fix coding style of the areas affected.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Make cpu_loop_exit() take a parameter for CPUState instead of relying
on global env.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

tb_invalidate_page_range() was intended to be used to invalidate an
area of a TB which the guest explicitly flushes from i-cache. However,
QEMU detects writes to code areas where TBs have been generated, so
his has never been useful.

Delete the function, adjust callers.
Reviewed-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The previous patch removed the need for parameter puc.
Is is now unused, so remove it.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NStefan Weil <weil@mail.berlios.de>

The "leon3_cache_control_int" (op_helper.c) function is called within leon3.c
which leads to segfault error with the global "env".

Now cache control is a CPU feature and everything is handled in op_helper.c.
Signed-off-by: NFabien Chouteau <chouteau@adacore.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more
information on http://www.gaisler.com).

Leon3 is made of multiple components available in the GrLib VHDL library.
Three devices are implemented: uart, timers and IRQ manager.
You can find code for these peripherals in the grlib_* files.
Signed-off-by: NFabien Chouteau <chouteau@adacore.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Fix several bugs in NaN handling:
 * e in fcmpe* only changes qNaN handling
 * FCC is unchanged if an exception is raised
 * clear previous FTT before setting it
Reported-by: NMateusz Loskot <mateusz@loskot.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Since commit 5a4bb580, Xorg crashes on
a Debian Etch image. The commit itself is fine, but it triggers a bug
due to wrong computation of flags for udiv(cc) and sdiv(cc).

This patch only compute cc_src2 for the cc version of udiv/sdiv. It
also moves the update of cc_dst and cc_op to the helper, as it is
faster doing it here when there is already an helper.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Use existing dump_mmu() to implement monitor command 'info tlb'.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- truncate second operand to 32bit
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- implemented block load/store primary/secondary with user privilege
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- use symbolic name for MMU index
v0->v1:
- change debug traces to DPRINTF_MMU
- fix debug trace function names
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- address masking for ldqf and stqf insns
- address masking for lddf and stdf insns
- address masking for translating ASI (Ultrasparc IIi)
v0->v1:
- move arch-specific code to helpers and drop more ifdefs at call sites
  using new helper asi_address_mask()
- change user emulation to use asi_address_mask()
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

SuperSPARC MMU Breakpoint Action register is used by OBP at boot

The patch allows booting Solaris and some other OS with
SPARCStation-20 OBP.
Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Accesses with _nucleus prefix are not available when building user
emulators:
  CC    sparc64-linux-user/op_helper.o
cc1: warnings being treated as errors
/src/qemu/target-sparc/op_helper.c: In function 'helper_ldda_asi':
/src/qemu/target-sparc/op_helper.c:3063: error: implicit declaration of function 'ldq_nucleus'

Avoid making such accesses. Fixes breakage by 54a3c0f0.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- change 128-bit atomic loads to reference nucleus context
v0->v1: dropped disassembler change
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers
  using value of DMMU primary and secondary context registers, so we need to
  flush softmmu translations when context registers are changed
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- refactor code to handle hpstate only if available for current cpu
- conditionally set hypervisor bit in hpstate register
- reorder softmmu indices so user accessable ones go first, translation context
  macros supervisor() and hypervisor() adjusted as well
- disable sparcv8 registers for TARGET_SPARC64
- fix cpu_mmu_index to use sparcv9 bits only
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Computing carry is trivial for some inputs.  By avoiding an
external function call, we generate near-optimal code for
the common cases of add+addx (double-word arithmetic) and
cmp+addx (a setcc pattern).
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Acked-by: NArtyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Use int32 types instead of target_ulong when computing ICC.  This
simplifies the generated code for 32-bit host and 64-bit guest.
Use the same simplified expressions for ICC as were already used
for XCC in carry flag generation.

Simplify the ADD carry generation to not consider a possible carry-in.
Use the more complex carry computation for ADDX only.  Use the same
carry algorithm for the XCC result of ADDX.  Similarly for SUB/SUBX.

Use the ADD carry generation functions for TADD/TADDTV.  Similarly
for SUB and TSUB/TSUBTV.

Tidy the code with respect to CODING_STYLE.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Return a target_ulong from compute_C_icc to match the width of the users.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- must use store address operand to demap, not store value
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier
flags could be stored to pstate.

Refactor PSR/CCR/CWP handling: concentrate the actual
functions to op_helper.c.

Thanks to Igor Kovalenko for reporting.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- increase max supported MMU modes to 6
- handle nucleus context asi
- handle secondary context asi
- handle non-faulting loads from secondary context
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

- match global tte against any context
- show global tte in MMU dump

v0->v1: added default case to switch statement in demap_tlb
- should fix gcc warning about uninitialized context variable
Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Use address_mask on both addr and addr+8 in both these routines,
rather than explicit masking with 0xffffffff.

Reformulate address_mask to return a result, rather than masking
a pass-by-reference argument.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Disable various target specific code that is only relevant to system emulation.
Signed-off-by: NPaul Brook <paul@codesourcery.com>

fix a potential null pointer dereference introduced in
commit	576c2cdcSigned-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

According to pages 9-31 - 9-34 of "SuperSPARC & MultiCache Controller
User's Manual":

1. "A lower priority fault may not overwrite the
    MFSR status of a higher priority fault."
2. The MFAR is overwritten according to the policy defined for the MFSR
3. The overwrite bit is asserted if the fault status register (MFSR)
   has been written more than once by faults of the same class
4. SuperSPARC will never place instruction fault addresses in the MFAR.

Implementation of points 1-3 allows booting Solaris 2.6 and 2.5.1.

v2: CODING_STYLE fixes
Signed-off-by: NArtyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>