- 17 3月, 2010 1 次提交
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由 Paul Brook 提交于
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 13 3月, 2010 2 次提交
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由 Andre Przywara 提交于
about half of target-i386/helper.c consist of CPUID related functions. Only one of them is a real TCG helper function. So move the whole CPUID stuff out of this into a separate file to get better maintainable parts. This is only code reordering and should not affect QEMU's functionality. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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由 Paul Brook 提交于
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: NPaul Brook <paul@codesourcery.com>
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- 01 3月, 2010 1 次提交
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由 Jason Wessel 提交于
If you make use of hw breakpoints on a 32bit x86 linux host, qemu will segmentation fault when processing the exception. The problem is that the value of env is stored in $ebp in the op_helper raise_exception() function, and it can have the wrong value when calling it from non generated code. It is possible to work around the problem by restoring the value of env before calling raise_exception() using a new helper function that takes (CPUState *) as one of the arguments. Signed-off-by: NJason Wessel <jason.wessel@windriver.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 24 2月, 2010 2 次提交
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由 Blue Swirl 提交于
helper.o(.text+0x11e0): In function `listflags': /src/qemu/target-i386/helper.c:661: warning: sprintf() is often misused, please use snprintf() Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 23 2月, 2010 1 次提交
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由 john cooper 提交于
This is a reimplementation of prior versions which adds the ability to define cpu models for contemporary processors. The added models are likewise selected via -cpu <name>, and are intended to displace the existing convention of "-cpu qemu64" augmented with a series of feature flags. A primary motivation was determination of a least common denominator within a given processor class to simplify guest migration. It is still possible to modify an arbitrary model via additional feature flags however the goal here was to make doing so unnecessary in typical usage. The other consideration was providing models names reflective of current processors. Both AMD and Intel have reviewed the models in terms of balancing generality of migration vs. excessive feature downgrade relative to released silicon. This version of the patch replaces the prior hard wired definitions with a configuration file approach for new models. Existing models are thus far left as-is but may easily be transitioned to (or may be overridden by) the configuration file representation. Proposed new model definitions are provided here for current AMD and Intel processors. Each model consists of a name used to select it on the command line (-cpu <name>), and a model_id which corresponds to a least common denominator commercial instance of the processor class. A table of names/model_ids may be queried via "-cpu ?model": : x86 Opteron_G3 AMD Opteron 23xx (Gen 3 Class Opteron) x86 Opteron_G2 AMD Opteron 22xx (Gen 2 Class Opteron) x86 Opteron_G1 AMD Opteron 240 (Gen 1 Class Opteron) x86 Nehalem Intel Core i7 9xx (Nehalem Class Core i7) x86 Penryn Intel Core 2 Duo P9xxx (Penryn Class Core 2) x86 Conroe Intel Celeron_4x0 (Conroe/Merom Class Core 2) : Also added is "-cpu ?dump" which exhaustively outputs all config data for all defined models, and "-cpu ?cpuid" which enumerates all qemu recognized CPUID feature flags. The pseudo cpuid flag 'check' when added to the feature flag list will warn when feature flags (either implicit in a cpu model or explicit on the command line) would have otherwise been quietly unavailable to a guest: # qemu-system-x86_64 ... -cpu Nehalem,check warning: host cpuid 0000_0001 lacks requested flag 'sse4.2|sse4_2' [0x00100000] warning: host cpuid 0000_0001 lacks requested flag 'popcnt' [0x00800000] A similar 'enforce' pseudo flag exists which in addition to the above causes qemu to error exit if requested flags are unavailable. Configuration data for a cpu model resides in the target config file which by default will be installed as: /usr/local/etc/qemu/target-<arch>.conf The format of this file should be self explanatory given the definitions for the above six models and essentially mimics the structure of the static x86_def_t x86_defs. Encoding of cpuid flags names now allows aliases for both the configuration file and the command line which reconciles some Intel/AMD/Linux/Qemu naming differences. This patch was tested relative to qemu.git. Signed-off-by: Njohn cooper <john.cooper@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 14 1月, 2010 1 次提交
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由 Gleb Natapov 提交于
Initialize KVM paravirt cpuid leaf and allow user to control guest visible PV features through -cpu flag. Signed-off-by: NGleb Natapov <gleb@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 11 1月, 2010 1 次提交
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由 Huang Ying 提交于
Now, if we inject a fatal MCE into guest OS, for example Linux, Linux will go panic and then reboot. But if we inject another MCE now, system will reset directly instead of go panic firstly, because MCG_STATUS.MCIP is set to 1 and not cleared after reboot. This is does not follow the behavior in real hardware. This patch fixes this via set env->mcg_status to 0 during system reset. Signed-off-by: NHuang Ying <ying.huang@intel.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 25 12月, 2009 1 次提交
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由 Gleb Natapov 提交于
Intel CPUs starting from pentium have apic. Lets advertise it. Signed-off-by: NGleb Natapov <gleb@redhat.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 14 12月, 2009 1 次提交
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由 Andre Przywara 提交于
The CPUID features QEMU presented to the guest were not up-to-date with QEMU's emulated feature set. Add the missing bits of recent (and not so recent) additions to QEMU's emulation engine. For stability reasons only the user mode usable bits are exposed for now, features like Monitor or CR8LEG are left out. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 08 12月, 2009 1 次提交
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由 Andre Przywara 提交于
The multicore CPUID code detects whether the guest is an Intel or an AMD CPU, because the Linux kernel is picky about the CmpLegacy bit. KVM by default passes through the host's vendor, which was not catched by the code. So fork out the vendor determining bits into a separate function to be used from both places and always get the real vendor. This fixes KVM's multicore setup on Intel CPUs. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Reported-by: NDietmar Maurer <dietmar@proxmox.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 07 11月, 2009 2 次提交
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Glauber Costa 提交于
There is absolutely no need to call reset functions when initializing devices. Since we are already registering them, calling qemu_system_reset() should suffice. Actually, it is what happens when we reboot the machine, and using the same process instead of a special case semantics will even allow us to find bugs easier. Furthermore, the fact that we initialize things like the cpu quite early, leads to the need to introduce synchronization stuff like qemu_system_cond. This patch removes it entirely. All we need to do is call qemu_system_reset() only when we're already sure the system is up and running I tested it with qemu (with and without io-thread) and qemu-kvm, and it seems to be doing okay - although qemu-kvm uses a slightly different patch. [ v2: user mode still needs cpu_reset, so put it in ifdef. ] [ v3: leave qemu_system_cond for now. ] Signed-off-by: NGlauber Costa <glommer@redhat.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 05 10月, 2009 2 次提交
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由 Juan Quintela 提交于
mce_banks is always MCE_BANKS_DEF * 4 in size, value never change CC: Huang Ying <ying.huang@intel.com> Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Juan Quintela 提交于
This makes the savevm code correct, and sign extensins gives us exactly what we need (namely, sign extend to 64 bits when used with 64bit addresess. Once there, change 0x100000 for 1 << 20, that maks all a20 use the same syntax. Signed-off-by: NJuan Quintela <quintela@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 02 10月, 2009 2 次提交
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由 Anthony Liguori 提交于
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 malc 提交于
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: Nmalc <av1474@comtv.ru>
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- 12 9月, 2009 3 次提交
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由 Jan Kiszka 提交于
cpu_synchronize_state already does this. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Blue Swirl 提交于
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235, f40d7537, 96555a96 and 3990d09a but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Gleb Natapov 提交于
Direct call to kvm_arch_get_registers() bypass logic in cpu_synchronize_state() Signed-off-by: NGleb Natapov <gleb@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 28 8月, 2009 4 次提交
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由 Andre Przywara 提交于
In addition to the TCG based qemu64 type let's introduce a kvm64 CPU type, which is the least common denominator of all KVM-capable x86-CPUs (based on Intel Pentium 4 Prescott). It can be used as a base type for migration. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
The CPUID level determines how many CPUID leafs are exposed to the guest. Some features (like multi-core) cannot be propagated without the proper level, but guests maybe confused by bogus entries in some leafs. So add level= and xlevel= to the list of -cpu options to allow the user to override the default settings. While at it, merge unnecessary local variables into one and allow hexadecimal arguments. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
Controlled by the enhanced -smp option set the CPUID bits to present the guest the desired topology. This is vendor specific, but (with the exception of the CMP_LEGACY bit) not conflicting, so we set all bits everytime. There is no real multithreading support for AMD CPUs, so report cores instead. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
Intel CPUs store the number of cores in CPUID leaf 4. So push the maxleaf value to 4 to allow the guests access to this leaf. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 24 8月, 2009 1 次提交
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由 Anthony Liguori 提交于
kqemu introduces a number of restrictions on the i386 target. The worst is that it prevents large memory from working in the default build. Furthermore, kqemu is fundamentally flawed in a number of ways. It relies on the TSC as a time source which will not be reliable on a multiple processor system in userspace. Since most modern processors are multicore, this severely limits the utility of kqemu. kvm is a viable alternative for people looking to accelerate qemu and has the benefit of being supported by the upstream Linux kernel. If someone can implement work arounds to remove the restrictions introduced by kqemu, I'm happy to avoid and/or revert this patch. N.B. kqemu will still function in the 0.11 series but this patch removes it from the 0.12 series. Paul, please Ack or Nack this patch. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 17 7月, 2009 4 次提交
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由 Anthony Liguori 提交于
-cpu host is not at all useful when using tcg. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Anthony Liguori 提交于
This causes a build break when !KVM. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
Since we recently do not disable 3DNOW! support anymore, we should avoid setting the bits in the default qemu64 CPU model to ease migration. TCG does not support it anyway and even AMD deprecates it's usage nowadays. If you want to use it in KVM, use the phenom, athlon or host CPU model. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 16 7月, 2009 1 次提交
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由 Jan Kiszka 提交于
This allows to set segment registers via gdb also in system emulation mode. Basic sanity checks are applied and nothing is changed if they fail. But screwing up the target via this interface will never be complicated, so I avoided being too paranoid here. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 10 7月, 2009 1 次提交
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由 Huang Ying 提交于
- MCE features are initialized when VCPU is intialized according to CPUID. - A monitor command "mce" is added to inject a MCE. - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE. aliguori: fix build for linux-user Signed-off-by: NHuang Ying <ying.huang@intel.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 02 7月, 2009 1 次提交
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由 Blue Swirl 提交于
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 30 6月, 2009 5 次提交
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由 Andre Przywara 提交于
KVM provides an in-kernel feature to disable CPUID bits that are not present in the current host. So there is no need here to duplicate this work. Additionally allows 3DNow! on capable processors, since the restriction seems to apply to QEMU/TCG only. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
If we want to trim the user provided CPUID bits for KVM to be not greater than that of the host, we should not remove the bits _after_ we sent them to the kernel. This fixes the masking of features that are not present on the host by moving the trim function and it's call from helper.c to kvm.c. It helps to use -cpu host. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
Although the guest's CPUID bits can be controlled in a fine grained way in QEMU, a simple way to inject the host CPU is missing. This is handy for KVM desktop virtualization, where one wants the guest to support the full host feature set. Introduce another CPU type called 'host', which will propagate the host's CPUID bits to the guest. Unwanted bits can still be turned off by using the existing syntax (-cpu host,-skinit) Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Andre Przywara 提交于
KVM defaults to the hypervisor CPUID bit to be set, whereas pure QEMU clears it. On some occasions one wants to set or clear it the other way round (for instance to get HyperV running inside a guest). Move the bit-set to be done before the command line parsing and enable it by default. One can disable it by using: -cpu qemu64,-hypervisor Fix some whitespace damage on the way. Signed-off-by: NAndre Przywara <andre.przywara@amd.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 22 6月, 2009 1 次提交
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由 Gleb Natapov 提交于
This should fix compilation problem in case of CONFIG_USER_ONLY. Currently INIT/SIPI is handled in the context of CPU that sends IPI. This patch changes this to handle them like all other events in a main cpu exec loop. When KVM will gain thread per vcpu capability it will be much more clear to handle those event by cpu thread itself and not modify one cpu's state from the context of the other. Signed-off-by: NGleb Natapov <gleb@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 17 6月, 2009 1 次提交
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由 Nitin A Kamble 提交于
As per the IA32 processor manual, the accessed bit is set to 1 in the processor state after reset. qemu pc cpu_reset code was missing this accessed bit setting. Signed-off-by: NNitin A Kamble <nitin.a.kamble@intel.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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