- 24 6月, 2012 5 次提交
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> [fix unwanted whitespace line in Makefile.target] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Blue Swirl 提交于
Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 02 2月, 2012 3 次提交
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由 Alexander Graf 提交于
This patch implements the msgsnd instruction. It is part of the Embedded.Processor Control specification and allows one CPU to IPI another CPU without going through an interrupt controller. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
This patch implements the msgclr instruction. It is part of the Embedded.Processor Control specification and clears pending doorbell interrupts on the current CPU. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used to flush TLB entries. It's the recommended way of flushing in virtualized environments. So far we got away without implementing it, but Linux for e500mc uses this instruction, so we better add it :). Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 03 6月, 2011 1 次提交
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由 Aurelien Jarno 提交于
target-ppc has been switched to softfloat only long ago, but a few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them. Cc: Alexander Graf <agraf@suse.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 12 5月, 2011 1 次提交
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由 Alexander Graf 提交于
Most of the code to support e500 style MMUs is already in place, but we're missing on some of the special TLB0-TLB1 handling code and slightly different TLB modification. This patch adds support for the FSL style MMU. Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 02 4月, 2011 4 次提交
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由 David Gibson 提交于
qemu already includes support for the popcntb instruction introduced in POWER5 (although it doesn't actually allow you to choose POWER5). However, the logic is slightly incorrect: it will generate results truncated to 32-bits when the CPU is in 32-bit mode. This is not normal for powerpc - generally arithmetic instructions on a 64-bit powerpc cpu will generate full 64 bit results, it's just that only the low 32 bits will be significant for condition codes. This patch corrects this nit, which actually simplifies the code slightly. In addition, this patch implements the popcntw and popcntd instructions added in POWER7, in preparation for allowing POWER7 as an emulated CPU. Signed-off-by: NDavid Gibson <dwg@au1.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
The PURR (Processor Utilization Resource Register) is a register found on recent POWER CPUs. The guts of implementing it at least enough to get by are already present in qemu, however some of the helper functions needed to actually wire it up are missing. This patch adds the necessary glue, so that the PURR can be wired up when we implement newer POWER CPU targets which include it. Signed-off-by: NDavid Gibson <dwg@au1.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
For a 64-bit PowerPC target, qemu correctly implements translation through the segment lookaside buffer. Likewise it supports the slbmte instruction which is used to load entries into the SLB. However, it does not emulate the slbmfee and slbmfev instructions which read SLB entries back into registers. Because these are only occasionally used in guests (mostly for debugging) we get away with it. However, given the recent SLB cleanups, it becomes quite easy to implement these, and thereby allow, amongst other things, a guest Linux to use xmon's command to dump the SLB. Signed-off-by: NDavid Gibson <dwg@au1.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 David Gibson 提交于
Currently the SLB information when emulating a PowerPC 970 is storeed in a structure with the unhelpfully named fields 'tmp' and 'tmp64'. While the layout in these fields does match the description of the SLB in the architecture document, it is not convenient either for looking up the SLB, or for emulating the slbmte instruction. This patch, therefore, reorganizes the SLB entry structure to be divided in the the "ESID related" and "VSID related" fields as they are divided in instructions accessing the SLB. In addition to making the code smaller and more readable, this will make it easier to implement for the 1TB segments used in more recent PowerPC chips. Signed-off-by: NDavid Gibson <dwg@au1.ibm.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 14 7月, 2010 1 次提交
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由 Aurelien Jarno 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 16 6月, 2010 1 次提交
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由 Richard Henderson 提交于
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 07 2月, 2010 1 次提交
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由 Aurelien Jarno 提交于
The recent transition to always have the DCR helper functions take 32 bit values broke the PPC64 target, as target_long became 64 bits there. This patch changes DCR helpers to target_long arguments, and cast the values to 32 bit when needed. Fixes PPC64 build with --enable-debug-tcg Based on a patch from Alexander Graf <agraf@suse.de> Reported-by: NStefan Weil <weil@mail.berlios.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 21 12月, 2009 1 次提交
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由 Alexander Graf 提交于
For what I know DCR is always 32 bits wide, so we should also use uint32_t to pass it along the stacks. This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, making it compile without --disable-werror Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 02 10月, 2009 2 次提交
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由 Anthony Liguori 提交于
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b. Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 malc 提交于
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: Nmalc <av1474@comtv.ru>
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- 16 4月, 2009 1 次提交
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162
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- 10 3月, 2009 1 次提交
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
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- 10 2月, 2009 7 次提交
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
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- 06 2月, 2009 1 次提交
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由 aurel32 提交于
Thanks to Nathan Froyd for noticing that. Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
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- 05 2月, 2009 1 次提交
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由 aurel32 提交于
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
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- 04 2月, 2009 3 次提交
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Do this so we can set float statuses once per mtvscr, rather than once per Altivec instruction. Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
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- 09 1月, 2009 4 次提交
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由 aurel32 提交于
Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
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- 05 1月, 2009 2 次提交
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
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由 aurel32 提交于
Signed-off-by: NNathan Froyd <froydnj@codesourcery.com> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
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