- 12 3月, 2013 2 次提交
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由 Andreas Färber 提交于
Move it to qom/cpu.h to avoid issues with include order. Change pc_acpi_smi_interrupt() opaque to X86CPU. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Andreas Färber 提交于
Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 05 3月, 2013 2 次提交
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由 Christoffer Dall 提交于
Add basic support for KVM on ARM architecture. Signed-off-by: NChristoffer Dall <cdall@cs.columbia.edu> [PMM: Minor tweaks and code cleanup, switch to ONE_REG] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Peter Maydell 提交于
Drop the CPUARMState* argument from bank_number(), since we only use it for passing to cpu_abort(). Use hw_error() instead. This avoids propagating further interfaces using env pointers. In the long term this function's callers need auditing to fix problems where badly behaved guests can pass invalid bank numbers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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- 24 2月, 2013 1 次提交
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由 Richard Henderson 提交于
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net> Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
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- 16 2月, 2013 2 次提交
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由 Andreas Färber 提交于
Ensures that a QOM-created ARMCPU is usable. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Andreas Färber 提交于
Turn arm_cpu_realize() into a QOM realize function, no longer called via cpu.h prototype. To maintain the semantics of cpu_init(), set realized = true explicitly in cpu_arm_init(). Move GDB coprocessor registration, CPU reset and vCPU initialization into the realizefn. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 31 1月, 2013 1 次提交
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由 Andreas Färber 提交于
In the initial conversion of CPU models to QOM types, model names were mapped 1:1 to type names. As a side effect this gained us a type "any", which is now a device. To avoid "-device any" silliness and to pave the way for compiling multiple targets into one executable, adopt a <name>-<arch>-cpu scheme. This leads to names like arm926-arm-cpu but is easiest to handle. No functional changes for -cpu arguments or -cpu ? output. Suggested-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 27 1月, 2013 1 次提交
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由 Andreas Färber 提交于
Consolidate model checking into a new arm_cpu_class_by_name(). If the name matches an existing type, also check whether that type is actually (a sub-type of) TYPE_ARM_CPU. This fixes, e.g., -cpu tmp105 asserting. Cc: qemu-stable <qemu-stable@nongnu.org> Acked-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 15 1月, 2013 1 次提交
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由 Andreas Färber 提交于
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 11 1月, 2013 1 次提交
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由 Alex_Rozenman@mentor.com 提交于
When do_interrupt_v7m is called with EXCP_SWI, the PC already points to the next instruction. Don't modify it here. Signed-off-by: NAlex Rozenman <Alex_Rozenman@mentor.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 12月, 2012 4 次提交
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由 Andreas Färber 提交于
This generalizes {ARM,M68k,Alpha}CPUListState to avoid declaring it for each target. Place it in cpu-common.h to avoid circular dependencies. Signed-off-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 24 10月, 2012 1 次提交
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由 Peter Maydell 提交于
Implement abs_i32 inline (with movcond) rather than using a helper function. Reviewed-by: NAurelien Jarno <aurelien@aurel32.net> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 10月, 2012 1 次提交
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由 Avi Kivity 提交于
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: NAvi Kivity <avi@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 16 9月, 2012 1 次提交
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由 Blue Swirl 提交于
Convert code load functions and switch to AREG0 free mode. Signed-off-by: NBlue Swirl <blauwirbel@gmail.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 9月, 2012 1 次提交
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由 Stefan Weil 提交于
Report from smatch: target-arm/helper.c:651 arm946_prbs_read(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8 target-arm/helper.c:661 arm946_prbs_write(6) error: buffer overflow 'env->cp15.c6_region' 8 <= 8 c7_region is an array with 8 elements, so the index must be less than 8. Signed-off-by: NStefan Weil <sw@weilnetz.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
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- 10 8月, 2012 1 次提交
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由 Peter Maydell 提交于
Fix a variety of typos in comments in target-arm files. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>
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- 12 7月, 2012 10 次提交
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由 Peter Maydell 提交于
Implement the actual table walk code for LPAE's long format translation tables. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must flush the TLB on writes to it Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement the different format of the PAR when long descriptor translation tables are in use. Note that we assume that get_phys_addr() returns a long-descriptor format DFSR value on failure if long descriptors are in use; this added subtlety tips the balance and makes it worth adding a comment documenting the API to get_phys_addr(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
In the implementation of get_phys_addr(), consistently use target_phys_addr_t to hold the physical address rather than uint32_t. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the full width of the register. Add the state fields for the top half and the 64 bit access path. Actual use of the top half of the register will come with the addition of the long-descriptor translation table format support. For the PAR we also need to correct the masking applied for 32 bit writes (there are no bits reserved if LPAE is implemented) and clear the high half when doing a 32 bit result VA-to-PA lookup. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; we only implement these as dummy RAZ versions; provide dummies for the 64 bit accesses as well. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add implementations of the AMAIR0 and AMAIR1 LPAE Auxiliary Memory Attribute Indirection Registers. These are implementation defined and we choose to implement them as RAZ/WI, matching the Cortex-A7 and Cortex-A15. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Implement the privileged-execute-never (PXN) translation table bit. It is implementation-defined whether this is implemented, so we give it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an LPAE feature flag and the implication logic, as a placeholder for actually implementing LPAE at a later date. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Fix a couple of cases where cp register names were copy-and-pasted. These are harmless since we don't use the name for anything (except debugging convenience) but could be confusing. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@samsung.com>
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由 Peter Maydell 提交于
Fix a copy-and-paste error in the register description for TTBR1 that meant it was a duplicate of TTBR0 rather than affecting the correct bit of CPU state. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 20 6月, 2012 10 次提交
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由 Peter Maydell 提交于
There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the final ID registers to the new cp15 scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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