- 17 6月, 2015 9 次提交
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由 Fam Zheng 提交于
Signed-off-by: NFam Zheng <famz@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Fam Zheng 提交于
Signed-off-by: NFam Zheng <famz@redhat.com> Reviewed-by: NJohn Snow <jsnow@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Fam Zheng 提交于
Signed-off-by: NFam Zheng <famz@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Petr Matousek 提交于
Due converting PIO to the new memory read/write api we no longer provide separate I/O region lenghts for read and write operations. As a result, reading from PIT Mode/Command register will end with accessing pit->channels with invalid index. Fix this by ignoring read from the Mode/Command register. This is CVE-2015-3214. Reported-by: NMatt Tait <matttait@google.com> Fixes: 0505bcde Cc: qemu-stable@nongnu.org Signed-off-by: NPetr Matousek <pmatouse@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Yossi Hindin 提交于
New options were added to enable Windows MSI installation package creation: Option --enable-guest-agent-msi, like the name suggests, enables building Windows MSI package for QEMU guest agent; option --disable-guest-agent-msi disables MSI package creation; by default, no MSI package is created Signed-off-by: NYossi Hindin <yhindin@redhat.com> Message-Id: <1430913460-13174-5-git-send-email-yhindin@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Yossi Hindin 提交于
The script enables building Windows MSI installation package on Linux with wixl tool. Signed-off-by: NYossi Hindin <yhindin@redhat.com> Message-Id: <1430913460-13174-4-git-send-email-yhindin@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Yossi Hindin 提交于
Debug printouts extended, helps installation troubleshooting Signed-off-by: NYossi Hindin <yhindin@redhat.com> Message-Id: <1430913460-13174-3-git-send-email-yhindin@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Yossi Hindin 提交于
Existing command line options include '-s install' and '-s uninstall'. These options install/uninstall both Windows QEMU GA service and optional VSS COM server. The QEMU GA Windows service allows always-on serving guest agent's QMP commands and VSS COM server enables guest agent integration with Volume Shadow Service. This commit introdices new options '-s vss-install' and '-s vss-uninstall', affecting only GA VSS COM server registration. The new options are useful for registering and unregistering the COM server during MSI installation, upgrade and uninstallation. Signed-off-by: NYossi Hindin <yhindin@redhat.com> Message-Id: <1430913460-13174-2-git-send-email-yhindin@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Pranith Kumar 提交于
qemu-log defaults to stderr when there is no '-D' option mentioned on command line. When '-D' option is specified, we also need to specify '-d' option for it to use the specified logfile. When using monitor to enable logging this is troublesome since there will be no '-d' option because of which monitor dumps the logs to stderr. Fix this by opening the log file when '-D' is specified on the command line. Also fix an ancient comment which does not hold true since changing location and log level has now been streamlined. Signed-off-by: NPranith Kumar <bobby.prani@gmail.com> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Luiz Capitulino <lcapitulino@redhat.com> CC: Markus Armbruster <armbru@redhat.com> CC: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1433946024-18439-1-git-send-email-bobby.prani@gmail.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 16 6月, 2015 31 次提交
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由 Peter Maydell 提交于
virtio-gpu: pci support bits and virtio-vga. # gpg: Signature made Mon Jun 15 13:55:19 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-vga-20150615-1: virtio-vga: add vgabios configuration virtio-vga: add '-vga virtio' support virtio-vga: add virtio gpu device with vga compatibility virtio-gpu-pci: add virtio pci support virtio-gpu: fix error message Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
linux-user patches for 2.4 softfreeze second spin with ioctl patch refreshed # gpg: Signature made Tue Jun 16 08:03:14 2015 BST using RSA key ID DE3C9BC0 # gpg: Good signature from "Riku Voipio <riku.voipio@iki.fi>" # gpg: aka "Riku Voipio <riku.voipio@linaro.org>" * remotes/riku/tags/pull-linux-user-20150616: linux-user: ioctl() command type is int linux-user: fix the breakpoint inheritance in spawned threads linux-user: use __get_user and __put_user in cmsg conversions linux-user: Fix length handling in host_to_target_cmsg linux-user: Use abi_ulong for TARGET_ELF_PAGESTART linux-user: Allocate thunk size dynamically Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Laurent Vivier 提交于
When executing a 64bit target chroot on 64bit host, the ioctl() command can mismatch. It seems the previous commit doesn't solve the problem in my case: 9c6bf9c7 linux-user: Fix ioctl cmd type mismatch on 64-bit targets For example, a ppc64 chroot on an x86_64 host: bash-4.3# ls Unsupported ioctl: cmd=0x80087467 Unsupported ioctl: cmd=0x802c7415 The origin of the problem is in syscall.c:do_ioctl(). static abi_long do_ioctl(int fd, abi_long cmd, abi_long arg) In this case (ppc64) abi_long is long (on the x86_64), and cmd = 0x0000000080087467 then if (ie->target_cmd == cmd) target_cmd is int, so target_cmd = 0x80087467 and to compare an int with a long, the sign is extended to 64bit, so the comparison is: if (0xffffffff80087467 == 0x0000000080087467) which doesn't match whereas it should. This patch uses int in the case of the target command type instead of abi_long. Signed-off-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NRiku Voipio <riku.voipio@linaro.org>
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由 Thierry Bultel 提交于
When a thread is spawned, cpu_copy re-initializes the bp & wp lists of current thread, instead of the ones of the new thread. The effect is that breakpoints are no longer hit. Signed-off-by: NThierry Bultel <thierry.bultel@basystemes.fr> Signed-off-by: NRiku Voipio <riku.voipio@linaro.org>
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由 Peter Maydell 提交于
The target payloads in cmsg conversions may not have the alignment required by the host. Using the get_user and put_user functions is the easiest way to handle this and also do the byte-swapping we require. (Note that prior to this commit target_to_host_cmsg was incorrectly using __put_user() rather than __get_user() for the SCM_CREDENTIALS conversion, which meant it wasn't getting the benefit of the misalignment handling.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRiku Voipio <riku.voipio@linaro.org>
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由 Peter Maydell 提交于
The previous code for handling payload length when converting cmsg structures from host to target had a number of problems: * we required the msg->msg_controllen to declare the buffer to have enough space for final trailing padding (we were checking against CMSG_SPACE), whereas the kernel does not require this, and common userspace code assumes this. (In particular, glibc's "try to talk to nscd" code that it will run on startup will receive a cmsg with a 4 byte payload and only allocate 4 bytes for it, which was causing us to do the wrong thing on architectures that need 8-alignment.) * we weren't correctly handling the fact that the SO_TIMESTAMP payload may be larger for the target than the host * we weren't marking the messages with MSG_CTRUNC when we did need to truncate a message that wasn't truncated by the host, but were instead logging a QEMU message; since truncation is always the result of a guest giving us an insufficiently sized buffer, we should report it to the guest as the kernel does and don't log anything Rewrite the parts of the function that deal with length to fix these issues, and add a comment in target_to_host_cmsg to explain why the overflow logging it does is a QEMU bug, not a guest issue. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRiku Voipio <riku.voipio@linaro.org>
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由 Peter Maydell 提交于
target-arm queue: * Handle "extended small page" descriptors correctly * Use extended address bits from supersection short descriptors * Update interrupt status for all cores in gic_update * Fix off-by-one in exynos4210_fimd bit-swap code * Remove stray unused 'pending_exception' field * Add Cortex-A53 KVM support * Fix reset value of REVIDR * Add AArch32 MIDR aliases for ARMv8 cores * MAINTAINERS update for ARM ACPI code * Trust the kernel's value of MPIDR if we're using KVM * Various pxa2xx device updates to avoid old APIs * Mark pxa2xx copro registers as ARM_CP_IO so -icount works * Correctly UNDEF Thumb2 DSP insns on Cortex-M3 * Initial work towards implementing PMSAv7 * Fix a reset order bug introduced recently * Correct "preferred return address" for cpreg access exceptions * Add ACPI SPCR table for the virt board # gpg: Signature made Mon Jun 15 18:19:34 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150615: (28 commits) hw/arm/virt-acpi-build: Add SPCR table ACPI: Add definitions for the SPCR table target-arm: Correct "preferred return address" for cpreg access exceptions hw/arm/boot: fix rom_reset notifier registration order arm: helper: rename get_phys_addr_mpu arm: Add has-mpu property arm: Implement uniprocessor with MP config arm: Refactor get_phys_addr FSR return mechanism arm: helper: Factor out CP regs common to [pv]msa arm: Don't add v7mp registers in MPU systems arm: Do not define TLBTR in PMSA systems target-arm: Add the THUMB_DSP feature hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState hw/arm/pxa2xx: Add reset method for pxa2xx_ssp hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMState hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO target-arm: Use the kernel's idea of MPIDR if we're using KVM MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer target-arm: add AArch32 MIDR aliases in ARMv8 ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Jones 提交于
Signed-off-by: NAndrew Jones <drjones@redhat.com> Tested-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Acked-by: NMichael S. Tsirkin <mst@redhat.com> Message-id: 1433929959-29530-3-git-send-email-drjones@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andrew Jones 提交于
SPCR is the Serial Port Console Redirection Table. See the document linked from http://uefi.org/acpi. For serial port types, "Interface Type", see the documentation for the Debug Port Table 2 (DBG2). Signed-off-by: NAndrew Jones <drjones@redhat.com> Tested-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NIgor Mammedov <imammedo@redhat.com> Acked-by: NMichael S. Tsirkin <mst@redhat.com> Message-id: 1433929959-29530-2-git-send-email-drjones@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The architecture defines that when taking an exception trying to access a coprocessor register, the "preferred return address" for the exception is the address of the instruction that caused the exception. Correct an off-by-4 error which meant we were returning the address after the instruction for traps which happened because of a failure of a runtime access-check function on an AArch32 register. (Traps caused by translate-time checkable permissions failures had the correct address, as did traps on AArch64 registers.) This fixes https://bugs.launchpad.net/qemu/+bug/1463338Reported-by: NRobert Buhren <robert@robertbuhren.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1433861440-30133-1-git-send-email-peter.maydell@linaro.org
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由 Eric Auger 提交于
commit ac9d32e3 had the consequence to register the do_cpu_reset after the rom_reset one. Hence they get executed in the wrong order. This commit restores the registration of do_cpu_reset in arm_load_kernel. Signed-off-by: NEric Auger <eric.auger@linaro.org> Reported-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434111582-9325-1-git-send-email-eric.auger@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This get_phys_addr is really for pmsav5. Rename it accordingly. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: bf4b019aa87d682a45998105ef8e4d4e97a5e117.1434066412.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
For processors that support MPUs, add a property to de-feature it. This is similar to the implementation of the EL3 feature. The processor definition in init sets ARM_FEATURE_MPU if it can support an MPU. post_init exposes the property, defaulting to true. If cleared by the instantiator, ARM_FEATURE_MPU is then removed at realize time. This is to support R profile processors that may or may-not have an MPU configured. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 632918cc48786e868ea18aa6bd12f70597994cad.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Add a boolean for indicating uniprocessors with MP extensions. This drives the U bit in MPIDR. Prepares support for Cortex-R5. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a70a80583df265e0174f01fa1fc92b33ea6d1db5.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Currently, the return code for get_phys_addr is overloaded for both success/fail and FSR value return. This doesn't handle the case where there is an error with a 0 FSR. This case exists in PMSAv7. So rework get_phys_addr and friends to return a success/failure boolean return code and populate the FSR via a caller provided uint32_t pointer. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a209e3d8ae00cda55260c970891f520210e26bad.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
V6+ PMSA and VMSA share some common registers that are currently in the VMSA definition block. Split them out into a new def that can be shared to PMSA. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 284db78a43c63c9bfbb60de539672c361bcb6af8.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
These registers are VMSA specific so they should be conditional on VMSA (i.e. !MPU). Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7bb8843e45f2635c6b7a583c5bb5da51ed4442a0.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
If doing a PMSA (MPU) system do not define the VMSA specific TLBTR CP. The def is done separately from VMSA registers group as it is affected by both the OMAP/STRONGARM RW errata and the MIDR backgrounding. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b03fea3840207edf633f5c9189400c3dd6a28d14.1434066412.git.peter.crosthwaite@xilinx.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Aurelio C. Remonda 提交于
Create an ARM_FEATURE_THUMB_DSP controlling the Thumb encodings of the 85 DSP instructions (these are all Thumb2). This is enabled for all non-M-profile CPUs with Thumb2 support, as the instructions are mandatory for R and A profiles. On M profile they are optional and not present in the Cortex-M3 (though they are in the M4). The effect of this commit is that we will now treat the DSP encodings as illegal instructions on M3, when previously we incorrectly implemented them. Signed-off-by: NAurelio C. Remonda <aurelioremonda@gmail.com> Message-id: 1434311355-26554-1-git-send-email-aurelioremonda@gmail.com [PMM: added clz/crc32/crc32c and default case to the early-decode switch; minor format/spacing fixups; reworded commit message a bit] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Update the pxa2xx_mmci device to stop using the old_mmio read and write callbacks in its MemoryRegionOps. This actually simplifies the code because the separate byte/halfword/word access functions were all calling into a single function to do the work anyway. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-6-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The pxa2xx-ssp device is already a QOM device but is still using the old-style register_savevm(); convert to VMState. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The pxa2xx_ssp device was missing a reset method; add one. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter..crosthwaite@xilinx.com> Message-id: 1434117989-7367-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
Convert the pxa2xx-fir device to QOM, including using a VMState for its migration info. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
The pxa2xx custom coprocessor registers in cp6 and cp14 do device accesses, so mark the non-constant regs as ARM_CP_IO so that icount works correctly and doesn't abort. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1434117989-7367-2-git-send-email-peter.maydell@linaro.org
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由 Pavel Fedin 提交于
When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: NShlomo Pongratz <shlomo.pongratz@huawei.com> Signed-off-by: NPavel Fedin <p.fedin@samsung.com> Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Add Shannon Zhao as the maintainer for the ARM ACPI Subsystem. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NClaudio Fontana <claudio.fontana@huawei.com> Acked-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1433248318-6076-1-git-send-email-shannon.zhao@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Sergey Fedorov 提交于
According to ARMv8 ARM, there are additional aliases to MIDR system register in AArch32 state. So add them to the list. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-3-git-send-email-serge.fdrv@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Sergey Fedorov 提交于
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-2-git-send-email-serge.fdrv@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Add cortex-a53 cpu support in machine virt, so it can be used for TCG and KVM. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1433207452-4512-3-git-send-email-shannon.zhao@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Since commit e3531026(target-arm: cpu64: Add support for Cortex-A53) has added Cortex-A53 cpu support for target-arm, this patch just enables it for kvm-arm. Here adding XGENE_POTENZA just makes the enum continuous. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1433207452-4512-2-git-send-email-shannon.zhao@linaro.org [PMM: Don't add the CPU types to cpus_to_try[]; this array only lists old CPUs which were supported in pre-PREFERRED_TARGET kernels] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
This isn't used by any of the code. In fact it looks like it was never used as it came in with ARMv7 support. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-id: 1434020015-8868-1-git-send-email-alex.bennee@linaro.org Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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