The addition of MO_AMASK means that places that used inverted masks
need to be changed to use positive masks, and places that failed to
mask the intended bits need updating.
Reviewed-by: NYongbok Kim <yongbok.kim@imgtec.com>
Tested-by: NYongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

The extra information is not yet used but it is now available.
This requires minor changes through all of the tcg backends.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

At the tcg opcode level, not at the tcg-op.h generator level.
This requires minor changes through all of the tcg backends,
but none of the cpu translators.
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

This is less about improved type checking than enabling a
subsequent change to the representation of labels.
Acked-by: NClaudio Fontana <claudio.fontana@huawei.com>
Tested-by: NClaudio Fontana <claudio.fontana@huawei.com>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Cc: Stefan Weil <sw@weilnetz.de>
Reviewed-by: NBastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

There are a variety of common cases for which we can use carry tricks to
avoid a conditional branch.  On very new hardware, use LOAD ON CONDITION
instead of a conditional branch.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Elides two insns from the sequence.  The resulting tlb compare
sequence is satisfyingly minimal:

	risbg  %r2,%r8,51,186,56
	risbg  %r3,%r8,61,178,0
	cg     %r3,904(%r10,%r2)
	lg     %r2,920(%r10,%r2)
	jlh    tlb_miss
Signed-off-by: NRichard Henderson <rth@twiddle.net>

That is, the old LDST_OPTIMIZATION.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

The INDEX_op_call case has just been obsoleted; the mov and movi
cases have not been reachable for years.  Attempt to document this
both in each tcg_out_op switch, and via TCG_OPF_NOT_PRESENT.

Because of the TCG_OPF_NOT_PRESENT change, this must be done for
all targets in a single commit.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

And use tcg pointer differencing functions as appropriate.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Now redundant with the type parameter to tcg_target_const_match.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Most 64-bit targets need to be able to ignore the high bits
of a TCG_TYPE_I32 value.
Suggested-by: NStuart Brady <sdb@zubnet.me.uk>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Commit c9baa30f failed to
delete all of the relevant code, leading to Werrors about
unused symbols.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>

No need to set up a SIGILL signal handler for detection anymore.

Remove a ton of sanity checks that must be true, given that we're
requiring a 64-bit build (the note about 31-bit KVM is satisfied
by configuring with TCI).
Signed-off-by: NRichard Henderson <rth@twiddle.net>

This is a no-op backend data implementation, for those targets that
are not currently using the load/store optimization path.

This is prepatory to always requiring these functions in all backends.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

The _cmmu helpers can be moved to exec-all.h.  The helpers that are
used from TCG will shortly need access to tcg_target_long so move
their declarations into tcg.h.

This requires minor include adjustments to all TCG backends.
Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Reviewed-by: NAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

We've got a compile-time check for the condition in exec/cpu-defs.h.
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: Nliguang <lig.fnst@cn.fujitsu.com>
Signed-off-by: NRichard Henderson <rth@twiddle.net>

When the TCG condition codes were re-organized last year,
we failed to update all of the "old-style" tests for unsigned.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

This can save one insn, if the constant has any bits in 32-63 set,
but no bits in 21-31 set.  It never results in more insns.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Since we're always in 64-bit mode, load address performs a full
64-bit add.  Use that for 3-address addition, as well as for
larger constant addends when we lack extended-immediates facility.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

This is immediately usable by the tlb lookup code.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Since we have a free temporary and can always just load the constant, we
ought to do so, rather than spending the same effort constraining the const.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

Signed-off-by: NRichard Henderson <rth@twiddle.net>

We only support 64-bit code generation for s390x.
Don't clutter the code with ifdefs that suggest otherwise.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

Set TCG_TARGET_CALL_STACK_OFFSET properly for the abi.  Allocate the
standard TCG_STATIC_CALL_ARGS_SIZE.  And while we're at it, allocate
space for CPU_TEMP_BUF_NLONGS.
Signed-off-by: NRichard Henderson <rth@twiddle.net>

The code to load the high 64 bits assumed that the insn used to
load the low 64 bits zero-extended.  Enforce that.