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  1. 30 9月, 2012 1 次提交
  3. 21 9月, 2012 2 次提交
  5. 29 8月, 2012 1 次提交
  7. 15 8月, 2012 3 次提交
  9. 10 7月, 2012 1 次提交
    • J
      apic: Defer interrupt updates to VCPU thread · 5d62c43a
      由 Jan Kiszka 提交于 
      KVM performs TPR raising asynchronously to QEMU, specifically outside
QEMU's global lock. When an interrupt is injected into the APIC and TPR
is checked to decide if this can be delivered, a stale TPR value may be
used, causing spurious interrupts in the end.

Fix this by deferring apic_update_irq to the context of the target VCPU.
We introduce a new interrupt flag for this, CPU_INTERRUPT_POLL. When it
is set, the VCPU calls apic_poll_irq before checking for further pending
interrupts. To avoid special-casing KVM, we also implement this logic
for TCG mode.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>
      5d62c43a
  11. 04 7月, 2012 1 次提交
  13. 29 6月, 2012 4 次提交
  15. 25 6月, 2012 1 次提交
  17. 05 6月, 2012 2 次提交
  19. 30 5月, 2012 1 次提交
    • E
      Expose CPUID leaf 7 only for -cpu host · 13526728
      由 Eduardo Habkost 提交于 
      Changes v2 -> v3;
  - Check for kvm_enabled() before setting cpuid_7_0_ebx_features

Changes v1 -> v2:
  - Use kvm_arch_get_supported_cpuid() instead of host_cpuid() on
    cpu_x86_fill_host().

  We should use GET_SUPPORTED_CPUID for all bits on "-cpu host"
  eventually, but I am not changing all the other CPUID leaves because
  we may not be able to test such an intrusive change in time for 1.1.

Description of the bug:

Since QEMU 0.15, the CPUID information on CPUID[EAX=7,ECX=0] is being
returned unfiltered to the guest, directly from the GET_SUPPORTED_CPUID
return value.

The problem is that this makes the resulting CPU feature flags
unpredictable and dependent on the host CPU and kernel version. This
breaks live-migration badly if migrating from a host CPU that supports
some features on that CPUID leaf (running a recent kernel) to a kernel
or host CPU that doesn't support it.

Migration also is incorrect (the virtual CPU changes under the guest's
feet) if you migrate in the opposite direction (from an old CPU/kernel
to a new CPU/kernel), but with less serious consequences (guests
normally query CPUID information only once on boot).

Fortunately, the bug affects only users using cpudefs with level >= 7.

The right behavior should be to explicitly enable those features on
[cpudef] config sections or on the "-cpu" command-line arguments. Right
now there is no predefined CPU model on QEMU that has those features:
the latest Intel model we have is Sandy Bridge.

I would like to get this fixed on 1.1, so I am submitting this patch,
that enables those features only if "-cpu host" is being used (as we
don't have any pre-defined CPU model that actually have those features).
After 1.1 is released, we can make those features properly configurable
on [cpudef] and -cpu configuration.

One problem is: with this patch, users with the following setup:
- Running QEMU 1.0;
- Using a cpudef having level >= 7;
- Running a kernel that supports the features on CPUID leaf 7; and
- Running on a CPU that supports some features on CPUID leaf 7
won't be able to live-migrate to QEMU 1.1. But for these users
live-migration is already broken (they can't live-migrate to hosts with
older CPUs or older kernels, already), I don't see how to avoid this
problem.
Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      13526728
  21. 25 4月, 2012 1 次提交
  23. 10 4月, 2012 1 次提交
  25. 15 3月, 2012 2 次提交
  27. 11 3月, 2012 1 次提交
  29. 18 2月, 2012 1 次提交
    • J
      target-i386: Add infrastructure for reporting TPR MMIO accesses · d362e757
      由 Jan Kiszka 提交于 
      This will allow the APIC core to file a TPR access report. Depending on
the accelerator and kernel irqchip mode, it will either be delivered
right away or queued for later reporting.

In TCG mode, we can restart the triggering instruction and can therefore
forward the event directly. KVM does not allows us to restart, so we
postpone the delivery of events recording in the user space APIC until
the current instruction is completed.

Note that KVM without in-kernel irqchip will report the address after
the instruction that triggered the access.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>
      d362e757
  31. 23 12月, 2011 1 次提交
  33. 25 10月, 2011 3 次提交
  35. 04 10月, 2011 1 次提交
  37. 21 9月, 2011 1 次提交
  39. 07 8月, 2011 1 次提交
  41. 05 8月, 2011 1 次提交
  43. 30 7月, 2011 1 次提交
    • B
      exec.h cleanup · 3e457172
      由 Blue Swirl 提交于 
      Move softmmu_exec.h include directives from target-*/exec.h to
target-*/op_helper.c. Move also various other stuff only used in
op_helper.c there.

Define global env in dyngen-exec.h.

For i386, move wrappers for segment and FPU helpers from user-exec.c
to op_helper.c. Implement raise_exception_err_env() to handle dynamic
CPUState. Move the function declarations to cpu.h since they can be
used outside of op_helper.c context.

LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and
env_to_regs().

ARM: make raise_exception() static.

Convert
#include "exec.h"
to
#include "cpu.h"
#include "dyngen-exec.h"
and remove now unused target-*/exec.h.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      3e457172
  45. 27 6月, 2011 2 次提交
  47. 19 6月, 2011 1 次提交
    • J
      kvm: x86: Save/restore FPU OP, IP and DP · 42cc8fa6
      由 Jan Kiszka 提交于 
      These FPU states are properly maintained by KVM but not yet by TCG. So
far we unconditionally set them to 0 in the guest which may cause
state corruptions, though not with modern guests.

To avoid breaking backward migration, use a conditional subsection that
is only written if any of the three fields is non-zero. The guest's
FNINIT clears them frequently, and cleared IA32_MISC_ENABLE MSR[2]
reduces the probability of non-zero values further so that this
subsection is not expected to restrict migration in any common scenario.
Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>
      42cc8fa6
  49. 14 6月, 2011 1 次提交
  51. 03 6月, 2011 1 次提交
  53. 01 6月, 2011 1 次提交
  55. 09 5月, 2011 2 次提交