VFP3 => VFP
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

M => THUMB_DIV
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

V7 => THUMB2
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

V6 && !M => AUXCR
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

V7 && M => V6
V7 && !M => V6K
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

V6K => V6
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

V6 => V5
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

V5 => V4T
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Return the correct value in the domain field in the cp15 DFSR
(C5) -- bug noticed during Xvisor development.
Signed-off-by: NJean-Christophe DUBOIS <jcd@tribudubois.net>
[Peter Maydell: reworded commit message]
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Don't call arm_translate_init() (which allocates TCG resources)
unless TCG is enabled.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com>

env is allocated in cpu_arm_init() with g_malloc0(), so free with g_free().
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Implement the fused multiply-accumulate instructions (VFMA, VFMS,
VFNMA, VFNMS) which are new in VFPv4.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Add support for UDIV and SDIV in ARM mode. This is a new optional
feature for A profile cores (Thumb mode has had UDIV and SDIV for
M profile cores for some time).
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Rename the ARM_FEATURE_DIV feature bit to _THUMB_DIV, to
make room for a new feature switch enabling DIV in the ARM
encoding. (Cores may implement either (a) no divide insns
(b) divide insns in Thumb encodings only (c) divide insns
in both ARM and Thumb encodings.)
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Indeed, the result is known to be always positive.
Signed-off-by: NChristophe Lyon <christophe.lyon@st.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The command line option is called -kernel, not -kenrel.

Cc: Paul Brook <paul@codesourcery.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAndreas Färber <andreas.faerber@web.de>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

qemu_malloc/qemu_free no longer exist after this commit.
Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>

Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.
Acked-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

The 1136r1 is actually a v6K core (unlike the 1136r0); mark it as such,
thus enabling the TLS registers, NOP hints, CLREX, half and byte wide
exclusive load/stores, etc.

The VA-to-PA translation registers are not present on 1136r1, so
introduce a new feature flag for them, which is enabled on 1176,
11MPCore and all v7 cores.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NJamie Iles <jamie@jamieiles.com>

Add support for v6K ARM1176JZF-S.  This core includes the VA<->PA
translation capability and security extensions.
Signed-off-by: NJamie Iles <jamie@jamieiles.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

The VMSAv7 remapping and access permissions were introduced in ARMv6K
and not ARMv7.
Signed-off-by: NJamie Iles <jamie@jamieiles.com>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Most exec-all.h include directives are now useless, remove them.
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>

Correct the decode of the register numbers for BASEPRI, BASEPRI_MAX
and FAULTMASK, according to "ARMv7-M Architecture Reference Manual"
issue D section "B5.2.3 MRS" and "B5.2.3 MSR".
Signed-off-by: NSebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Newer Linux kernels assume the existence of the performance counter
cp15 registers. Provide a minimal implementation of these registers.
We support no events. This should be compliant with the ARM ARM,
except that we don't implement the cycle counter.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Make the VFP binop helper functions take a pointer to the fp status, not
the entire CPUState. This will allow us to use them for Neon operations too.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>

Signed-off-by: NAlex Zuepke <azuepke@sysgo.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The Neon versions of int-float conversions must use the "standard FPSCR"
rather than the default FPSCR. Implement this by having the helper
functions take a pointer to the appropriate float_status value rather
than simply taking a pointer to the entire CPUState, and making
translate.c pass a pointer to vfp.fp_status or vfp.standard_fp_status
appropriately for whether the instruction being translated is Neon
or VFP.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

On ARM the architecture mandates that when an output denormal is flushed to
zero we must set the FPSCR UFC (underflow) bit, so map softfloat's
float_flag_output_denormal accordingly.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The helpers for VRECPE.F32, VSQRTE.F32, VRECPS and VRSQRTS handle denormals
as special cases, so we must set the InputDenormal exception flag ourselves.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The functions which do the core estimation algorithms for the VRSQRTE
and VRECPE instructions should not set floating point exception flags,
so use a local fp status for doing these calculations.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

When we catch the special case of an input NaN in ARM float to int
helper functions, set the Invalid flag as well as returning the
correct result.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation.
Implemented:
 - IRQs
 - GPIO
 - PPC
 - RTC
 - UARTs (no IrDA/etc.)
 - OST reused from pxa25x

Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the
hw/strongarm.c
Signed-off-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

This provides a consistent naming scheme across all targets.
Signed-off-by: NLluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

helpfull -> helpful
usefull -> useful
cotrol -> control

and a grammar fix.
Signed-off-by: NStefan Weil <weil@mail.berlios.de>
Signed-off-by: NStefan Hajnoczi <stefanha@linux.vnet.ibm.com>

The ARM architecture mandates that we detect tininess before rounding,
so set the softfloat fp_status up appropriately.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Currently target-arm/ assumes at least ARMv5 core. Add support for
handling also ARMv4/ARMv4T. This changes the following instructions:

BX(v4T and later)

BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,
MRRC2, PLD QADD, QDADD, QDSUB, QSUB, STRD, SMLAxy, SMLALxy, SMLAWxy,
SMULxy, SMULWxy, STC2 (v5 and later)

All instructions that are "v5TE and later" are also bound to just v5, as
that's how it was before.

This patch doesn _not_ include disabling of cp15 access and base-updated
data abort model (that will be required to emulate chips based on a
ARM7TDMI), because:
* no ARM7TDMI chips are currently emulated (or planned)
* those features aren't strictly necessary for my purposes (SA-1 core
  emulation).

All v5 models are handled as they are v5T. Internally we still have a
check if the model is a v5(T) or v5TE, but as all emulated cores are
v5TE, those two cases are simply aliased (for now).

Patch is heavily based on patch by Filip Navara <filip.navara@gmail.com>
which in turn is based on work by Ulrich Hecht <uli@suse.de> and Vincent
Sanders <vince@kyllikki.org>.
Signed-off-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Reviewed-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Correct the argument and return types for the float<->int conversion helper
functions so that integer arguments and return values are declared as
uint32_t/uint64_t, not float32/float64. This allows us to remove the
hand-rolled functions which were doing bitwise copies between the types
via unions.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NNathan Froyd <froydnj@codesourcery.com>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

The preferred way to create a constant floating point value is to use
make_float32() rather than doing a runtime int32_to_float32().
Convert the code in the VRSQRTS helper to work this way.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Correct the handling of edge cases for the VRECPS instruction:
 * this is a Neon instruction so uses the "standard FPSCR value"
 * (zero, inf) is a special case which returns 2.0
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

Fix the signed modulo arithmetic helpers for the v6media
instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set
the GE bits correctly (based on the result of the add or subtract
before it is truncated to 16 bits, not after).
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>