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  1. 02 7月, 2012 2 次提交
  3. 05 6月, 2012 1 次提交
  5. 04 3月, 2012 1 次提交
    • S
      w64: Fix size of ram_addr_t · 53576999
      由 Stefan Weil 提交于 
      ram_addr_t must be large enough to address any address of the host.

For hosts with sizeof(unsigned long) == sizeof(void *), this patch
changes nothing. All currently supported hosts fall into this category.

For w64 hosts, sizeof(unsigned long) is 4 while sizeof(void *) is 8,
so the use of uintptr_t is needed.
Signed-off-by: NStefan Weil <sw@weilnetz.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      53576999
  7. 04 1月, 2012 8 次提交
  9. 19 12月, 2011 2 次提交
  11. 15 12月, 2011 1 次提交
  13. 02 12月, 2011 1 次提交
  15. 29 7月, 2011 1 次提交
  17. 26 7月, 2011 1 次提交
  19. 21 7月, 2011 1 次提交
  21. 17 7月, 2011 1 次提交
  23. 13 7月, 2011 1 次提交
    • A
      exec: add endian specific phys ld/st functions · 1e78bcc1
      由 Alexander Graf 提交于 
      Device code some times needs to access physical memory and does that
through the ld./st._phys functions. However, these are the exact same
functions that the CPU uses to access memory, which means they will
be endianness swapped depending on the target CPU.

However, devices don't know about the CPU's endianness, but instead
access memory directly using their own interface to the memory bus,
so they need some way to read data with their native endianness.

This patch adds _le and _be functions to ld./st._phys.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      1e78bcc1
  25. 19 6月, 2011 1 次提交
    • S
      exec.c: refactor cpu_physical_memory_map · 38bee5dc
      由 Stefano Stabellini 提交于 
      Introduce qemu_ram_ptr_length that takes an address and a size as
parameters rather than just an address.

Refactor cpu_physical_memory_map so that we call qemu_ram_ptr_length only
once rather than calling qemu_get_ram_ptr one time per page.
This is not only more efficient but also tries to simplify the logic of
the function.
Currently we are relying on the fact that all the pages are mapped
contiguously in qemu's address space: we have a check to make sure that
the virtual address returned by qemu_get_ram_ptr from the second call on
is consecutive. Now we are making this more explicit replacing all the
calls to qemu_get_ram_ptr with a single call to qemu_ram_ptr_length
passing a size argument.
Signed-off-by: NStefano Stabellini <stefano.stabellini@eu.citrix.com>
CC: agraf@suse.de
CC: anthony@codemonkey.ws
Signed-off-by: NAlexander Graf <agraf@suse.de>
      38bee5dc
  27. 04 6月, 2011 1 次提交
  29. 08 5月, 2011 1 次提交
  31. 13 4月, 2011 1 次提交
  33. 07 4月, 2011 1 次提交
  35. 15 3月, 2011 1 次提交
  37. 14 2月, 2011 1 次提交
  39. 11 12月, 2010 1 次提交
    • A
      exec: introduce endianness swapped mmio · dd310534
      由 Alexander Graf 提交于 
      The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm aware of). Some
are big endian (special system devices) and a very little fraction is
target native endian (fw_cfg).

So instead of assuming every device to be native endianness, let's move
to a model where the device tells us which endianness it's in.

That way we can compile the devices only once and get rid of all the ugly
swap will be done by the underlying layer.

For the same of readability, this patch only introduces the helper framework
but doesn't allow the registering code to set its endianness yet.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      dd310534
  41. 03 12月, 2010 1 次提交
  43. 21 10月, 2010 1 次提交
  45. 11 8月, 2010 1 次提交
  47. 06 7月, 2010 1 次提交
  49. 25 4月, 2010 1 次提交
  51. 10 4月, 2010 1 次提交
  53. 02 4月, 2010 1 次提交
    • A
      tcg: initial ia64 support · 477ba620
      由 Aurelien Jarno 提交于 
      A few words about design choices:
* On IA64, instructions should be grouped by bundle, and dependencies
  between instructions declared. A first version of this code tried to
  schedule instructions automatically, but was very complex and too
  invasive for the current common TCG code (ops not ending at
  instruction boundaries, code retranslation breaking already generated
  code, etc.)  It was also not very efficient, as dependencies between
  TCG ops is not available.
  Instead the option taken by the current implementation does not try
  to fill the bundle by scheduling instructions, but by providing ops
  not available as an ia64 instruction, and by offering 22-bit constant
  loading for most of the instructions. With both options the bundle are
  filled at approximately the same level.

* Up to 128 registers can be affected to a function on IA64, but TCG
  limits this number to 64, which is actually more than enough. The
  register affectation is the following:
  - r0: used to map a constant argument with value 0
  - r1: global pointer
  - r2, r3: internal use
  - r4 to r6: not used to avoid saving them
  - r7: env structure
  - r8 to r11: free for TCG (call clobbered)
  - r12: stack pointer
  - r13: thread pointer
  - r14 to r31: free for TCG (call clobbered)
  - r32: reserved (return address)
  - r33: reserved (PFS)
  - r33 to r63: free for TCG

* The IA64 architecture has only 64-bit registers and no 32-bit
  instructions (the only exception being cmp4). Therefore 64-bit
  registers and instructions are used for 32-bit ops. The adopted
  strategy is the same as the ABI, that is the higher 32 bits are
  undefined. Most ops (and, or, add, shl, etc.) can directly use
  the 64-bit registers, while some others have to sign-extend (sar,
  div, etc.) or zero-extend (shr, divu, etc.) the register first.
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      477ba620
  55. 22 3月, 2010 1 次提交
  57. 13 3月, 2010 1 次提交
  59. 10 2月, 2010 1 次提交
  61. 02 10月, 2009 1 次提交