- 20 6月, 2012 6 次提交
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由 Peter Maydell 提交于
Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 05 6月, 2012 2 次提交
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由 Andreas Färber 提交于
In commit 1bba0dc9 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Andreas Färber 提交于
Commit 3c30dd5a (target-arm: Move reset handling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacing cpu_state_reset() with cpu_reset(). Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NPeter Maydell <peter.maydell@linaro.org>
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- 27 4月, 2012 1 次提交
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由 Andreas Färber 提交于
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to obtain an ARMCPU through arm_env_get_cpu() in machine init code. This requires to adjust the inclusion site of cpu-qom.h and in turn, forward-looking, to homogenize its include order. cpu_init() must still return a CPUARMState for backwards and cross-target compatibility, so adjust the cpu_init macro. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 22 4月, 2012 13 次提交
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由 Peter Maydell 提交于
Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move feature register value setup to per-CPU init functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
None of the machines in QEMU offer a JTAG debug interface, so this info was unused. Further, the PXA250 ID contradicts the February 2002 Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the MVFR* VFP feature register values to ARMCPU, so they are set up by the implementation-specific instance init functions rather than in cpu_reset_model_id(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the reset FPSID to the ARMCPU struct, and set it in the per-implementation instance init function. At reset we then just copy the reset value into the CPUARMState field. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the setting of the feature bits from cpu_reset_model_id() to each CPU's instance init function. This requires us to move the features field in CPUARMState so that it is not cleared on reset. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Register subclasses for each ARM CPU implementation. Let arm_cpu_list() enumerate CPU subclasses in alphabetical order, except for special value "any". Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the CPUID (aka MIDR, Main ID Register) value in the class. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 4月, 2012 1 次提交
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由 Paul Brook 提交于
Add support for ARM BE8 userspace binaries. i.e. big-endian data and little-endian code. In principle LE8 mode is also possible, but AFAIK has never actually been implemented/used. System emulation doesn't have any useable big-endian board models, but should in principle work once you fix that. Dynamic endianness switching requires messing with data accesses, preferably with TCG cooperation, and is orthogonal to BE8 support. Signed-off-by: NPaul Brook <paul@codesourcery.com> [PMM: various changes, mostly as per my suggestions in code review: * rebase * use EF_ defines rather than hardcoded constants * make bswap_code a bool for future VMSTATE macro compatibility * update comment in cpu.h about TB flags bit field usage * factor out load-code-and-swap into arm_ld*_code functions and get_user_code* macros * fix stray trailing space at end of line * added braces in disas.c to satisfy checkpatch ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRiku Voipio <riku.voipio@linaro.org>
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- 30 3月, 2012 1 次提交
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由 Andrew Towers 提交于
This patch replaces the ARM_FEATURE_VFP3 test when reading MVFR registers with a test for a new feature flag ARM_FEATURE_MVFR, and sets this feature for all ARMv6K cores (ARM1156 is not a v6K core, yet supports MVFR; qemu does not support ARM1156 at this time.) MVFR0 and MVFR1 were introduced in ARM1136JF-S r1p0 (ARMv6K, VFPv2) and are present in ARM1156T2F-S (non-v6K), ARM1176JZF-S, ARM11MPCore and newer cores. Reference: ARM DDI 0211H, 0290G, 0301H, 0360E. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Ffbefjag.html Without this change, the linux kernel will not boot with VFP support enabled under ARM1176 system emulation, due to the unconditional use of MVFR1 at the end of vfp_init() in arch/arm/vfp/vfpmodule.c: VFP support v0.3: implemetor 41 architecture 1 part 20 variant b rev 5 Internal error: Oops - undefined instruction: 0 [#1] Signed-off-by: NAndrew Towers <atowers@gmail.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 3月, 2012 2 次提交
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由 Andreas Färber 提交于
Introduce only one non-abstract type TYPE_ARM_CPU and do not touch cp15 registers to not interfere with Peter's ongoing remodelling. Embed CPUARMState as first (additional) field of ARMCPU. Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andreas Färber 提交于
It's unused, so no need to QOM'ify it later. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 16 3月, 2012 2 次提交
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由 Peter Maydell 提交于
When taking an exception for an M profile core, we must clear the IT bits. Since the IT bits are cached in env->condexec_bits we must clear them there: writing the bits in env->uncached_cpsr has no effect. (Reported as LP:944645.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Fix a typo in handling of the ARM946 cp15 c5 c0 0 1 handling (instruction access permission bits) that meant it would return the data access permission bits by mistake. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 15 3月, 2012 2 次提交
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由 Andreas Färber 提交于
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NAnthony Liguori <aliguori@us.ibm.com> Acked-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Andreas Färber 提交于
Frees the identifier cpu_reset for QOM CPUs (manual rename). Don't hide the parameter type behind explicit casts, use static functions with strongly typed argument to indirect. Signed-off-by: NAndreas Färber <afaerber@suse.de> Reviewed-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 29 2月, 2012 1 次提交
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由 Stefan Weil 提交于
Remove some include statements which are not needed. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NStefan Weil <sw@weilnetz.de>
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- 17 2月, 2012 2 次提交
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由 Peter Maydell 提交于
Since target-arm has some CPUState fields for which we take the approach of baking assumptions about them into translated code and then calling tb_flush() when the fields change, we must also tb_flush on CPU reset, because reset is a change of those fields. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com>
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由 Peter Maydell 提交于
The correct FPSID for the Cortex-A9 (according to the TRM) is 0x41033090 for the r0p0 that we claim to model. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndrzej Zaborowski <andrew.zaborowski@intel.com>
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- 25 1月, 2012 5 次提交
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由 Peter Maydell 提交于
Add a definition of a Cortex-A15 CPU. Note that for the moment we do not implement any of: * Large Physical Address Extensions (LPAE) * Virtualization Extensions * Generic Timer * TrustZone (this is also true of our existing Cortex-A9 model, etc) This CPU model is sufficient to boot a Linux kernel which has been compiled for an A15 without LPAE enabled. Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add a dummy implementation of the cp15 registers for the generic timer (found in the Cortex-A15), just sufficient for Linux to decide that it can't use it. This requires at least CNTP_CTL and CNTFRQ to be implemented as RAZ/WI; we RAZ/WI all of c14. Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Mark Langsdorf 提交于
Long term, the config_base_register will be a QDM parameter. In the meantime, models that use it need to be able to preserve it across cpu_reset() calls. Signed-off-by: NMark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
In the helper routines for VCVT float-to-int conversions, add an explicit cast rather than relying on the softfloat int32 type being exactly 32 bits wide (which it is not guaranteed to be). Without this, if the softfloat type was 64 bits wide we would get zero-extension of the 32 bit value from the ARM register rather than sign-extension, since TCG i32 values are passed as uint32_t. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Fix some bugs in the implementation of the TLB invalidate operations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since tlb_flush() currently ignores that argument, but is semantically incorrect * 'invalidate by address for all ASIDs' was implemented as flushing the whole TLB, which invalidates much more than strictly necessary. Use tlb_flush_page() instead. We also annotate the ops with the ARM ARM official acronyms. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 14 1月, 2012 1 次提交
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由 Rob Herring 提交于
Signed-off-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NMark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 05 1月, 2012 1 次提交
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由 Mark Langsdorf 提交于
Add dummy register support for the cp15, CRn=c15 registers. config_base_register and power_control_register currently default to 0, but may have improved support after the QOM CPU patches are finished. Signed-off-by: NMark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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