1. 01 2月, 2013 1 次提交
    • A
      target-m68k: Rename CPU subtypes · 7a9f812b
      Andreas Färber 提交于
      In the initial conversion of CPU models to QOM types, model names were
      mapped 1:1 to type names. As a side effect this gained us a type "any",
      which is now a device.
      
      To avoid "-device any" silliness and to pave the way for compiling
      multiple targets into one executable, adopt a <name>-<arch>-cpu scheme.
      
      No functional changes for -cpu arguments or -cpu ? output.
      Signed-off-by: NAndreas Färber <afaerber@suse.de>
      7a9f812b
  2. 27 1月, 2013 1 次提交
  3. 19 12月, 2012 2 次提交
  4. 23 10月, 2012 1 次提交
    • A
      Rename target_phys_addr_t to hwaddr · a8170e5e
      Avi Kivity 提交于
      target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
      reserved) and its purpose doesn't match the name (most target_phys_addr_t
      addresses are not target specific).  Replace it with a finger-friendly,
      standards conformant hwaddr.
      
      Outstanding patchsets can be fixed up with the command
      
        git rebase -i --exec 'find -name "*.[ch]"
                              | xargs s/target_phys_addr_t/hwaddr/g' origin
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      a8170e5e
  5. 05 6月, 2012 1 次提交
    • A
      Kill off cpu_state_reset() · b7e516ce
      Andreas Färber 提交于
      In commit 1bba0dc9 cpu_reset()
      was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()
      that would operate on QOM objects.
      
      All callers have been updated except for one in target-mips, so drop all
      implementations except for the one in target-mips and move the
      declaration there until MIPSCPU reset can be fully QOM'ified.
      Signed-off-by: NAndreas Färber <afaerber@suse.de>
      Acked-by: Michael Walle <michael@walle.cc> (for lm32)
      Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
      Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris)
      Acked-by: Alexander Graf <agraf@suse.de> (for ppc)
      Acked-by: NBlue Swirl <blauwirbel@gmail.com>
      b7e516ce
  6. 30 4月, 2012 4 次提交
  7. 15 3月, 2012 2 次提交
  8. 29 2月, 2012 1 次提交
  9. 21 8月, 2011 1 次提交
  10. 07 8月, 2011 1 次提交
  11. 27 6月, 2011 1 次提交
  12. 08 5月, 2011 1 次提交
  13. 02 1月, 2011 1 次提交
  14. 30 10月, 2010 1 次提交
  15. 24 4月, 2010 1 次提交
  16. 17 3月, 2010 1 次提交
    • P
      Large page TLB flush · d4c430a8
      Paul Brook 提交于
      QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
      pages then we effectively split these into multiple smaller pages, and
      populate the corresponding TLB entries on demand.
      
      When the guest invalidates the TLB by virtual address we must invalidate
      all entries covered by the large page.  However the address used to
      invalidate the entry may not be present in the QEMU TLB, so we do not
      know which regions to clear.
      
      Implementing a full vaiable size TLB is hard and slow, so just keep a
      simple address/mask pair to record which addresses may have been mapped by
      large pages.  If the guest invalidates this region then flush the
      whole TLB.
      Signed-off-by: NPaul Brook <paul@codesourcery.com>
      d4c430a8
  17. 13 3月, 2010 1 次提交
  18. 02 10月, 2009 2 次提交
  19. 17 7月, 2009 1 次提交
  20. 10 5月, 2009 1 次提交
  21. 25 4月, 2009 1 次提交
  22. 08 3月, 2009 1 次提交
  23. 06 2月, 2009 1 次提交
  24. 27 1月, 2009 1 次提交
  25. 05 1月, 2009 1 次提交
  26. 01 12月, 2008 1 次提交
  27. 12 10月, 2008 1 次提交
  28. 25 5月, 2008 1 次提交
  29. 12 4月, 2008 1 次提交
  30. 09 12月, 2007 1 次提交
  31. 18 11月, 2007 1 次提交
  32. 13 11月, 2007 1 次提交
  33. 10 11月, 2007 1 次提交
  34. 14 10月, 2007 1 次提交
    • J
      Replace is_user variable with mmu_idx in softmmu core, · 6ebbf390
      j_mayer 提交于
        allowing support of more than 2 mmu access modes.
      Add backward compatibility is_user variable in targets code when needed.
      Implement per target cpu_mmu_index function, avoiding duplicated code
        and #ifdef TARGET_xxx in softmmu core functions.
      Implement per target mmu modes definitions. As an example, add PowerPC
        hypervisor mode definition and Alpha executive and kernel modes definitions.
      Optimize PowerPC case, precomputing mmu_idx when MSR register changes
        and using the same definition in code translation code.
      
      
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
      6ebbf390