- 10 6月, 2019 1 次提交
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由 Richard Henderson 提交于
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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- 03 6月, 2019 1 次提交
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由 Wanpeng Li 提交于
The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR IA32_MISC_ENABLE MWAIT bit and as userspace has control of them both, it is userspace's job to configure both bits to match on the initial setup. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: NWanpeng Li <wanpengli@tencent.com> Message-Id: <1557813999-9175-1-git-send-email-wanpengli@tencent.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 11 5月, 2019 1 次提交
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由 Richard Henderson 提交于
We do not support probing, but we do not need it yet either. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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- 26 4月, 2019 1 次提交
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由 Pu Wen 提交于
Add a new base CPU model called 'Dhyana' to model processors from Hygon Dhyana(family 18h), which derived from AMD EPYC(family 17h). The following features bits have been removed compare to AMD EPYC: aes, pclmulqdq, sha_ni The Hygon Dhyana support to KVM in Linux is already accepted upstream[1]. So add Hygon Dhyana support to Qemu is necessary to create Hygon's own CPU model. Reference: [1] https://git.kernel.org/tip/fec98069fb72fb656304a3e52265e0c2fc9adf87Signed-off-by: NPu Wen <puwen@hygon.cn> Message-Id: <1555416373-28690-1-git-send-email-puwen@hygon.cn> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 19 4月, 2019 3 次提交
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由 Markus Armbruster 提交于
CPUClass method dump_statistics() takes an fprintf()-like callback and a FILE * to pass to it. Most callers pass fprintf() and stderr. log_cpu_state() passes fprintf() and qemu_log_file. hmp_info_registers() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The callback gets passed around a lot, which is tiresome. The type-punning around monitor_fprintf() is ugly. Drop the callback, and call qemu_fprintf() instead. Also gets rid of the type-punning, since qemu_fprintf() takes NULL instead of the current monitor cast to FILE *. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-15-armbru@redhat.com>
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由 Markus Armbruster 提交于
x86_cpu_dump_local_apic_state() takes an fprintf()-like callback and a FILE * to pass to it, and so do its helper functions. Its only caller hmp_info_local_apic() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The type-punning is ugly. Drop the callback, and call qemu_printf() instead. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-12-armbru@redhat.com>
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由 Markus Armbruster 提交于
The various TARGET_cpu_list() take an fprintf()-like callback and a FILE * to pass to it. Their callers (vl.c's main() via list_cpus(), bsd-user/main.c's main(), linux-user/main.c's main()) all pass fprintf() and stdout. Thus, the flexibility provided by the (rather tiresome) indirection isn't actually used. Drop the callback, and call qemu_printf() instead. Calling printf() would also work, but would make the code unsuitable for monitor context without making it simpler. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-10-armbru@redhat.com> Reviewed-by: NDr. David Alan Gilbert <dgilbert@redhat.com>
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- 11 3月, 2019 1 次提交
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由 Luwei Kang 提交于
Intel Processor Trace required CPUID[0x14] but the cpuid_level have no change when create a kvm guest with e.g. "-cpu qemu64,+intel-pt". Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NLuwei Kang <luwei.kang@intel.com> Message-Id: <1548805979-12321-1-git-send-email-luwei.kang@intel.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 05 2月, 2019 1 次提交
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由 Robert Hoo 提交于
This reverts commit 5131dc43. For new instruction 'PCONFIG' will not be exposed to guest. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1545227081-213696-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 14 1月, 2019 2 次提交
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由 Eduardo Habkost 提交于
Some downstream distributions of QEMU set host-phys-bits=on by default. This worked very well for most use cases, because phys-bits really didn't have huge consequences. The only difference was on the CPUID data seen by guests, and on the handling of reserved bits. This changed in KVM commit 855feb673640 ("KVM: MMU: Add 5 level EPT & Shadow page table support"). Now choosing a large phys-bits value for a VM has bigger impact: it will make KVM use 5-level EPT even when it's not really necessary. This means using the host phys-bits value may not be the best choice. Management software could address this problem by manually configuring phys-bits depending on the size of the VM and the amount of MMIO address space required for hotplug. But this is not trivial to implement. However, there's another workaround that would work for most cases: keep using the host phys-bits value, but only if it's smaller than 48. This patch makes this possible by introducing a new "-cpu" option: "host-phys-bits-limit". Management software or users can make sure they will always use 4-level EPT using: "host-phys-bits=on,host-phys-bits-limit=48". This behavior is still not enabled by default because QEMU doesn't enable host-phys-bits=on by default. But users, management software, or downstream distributions may choose to change their defaults using the new option. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20181211192527.13254-1-ehabkost@redhat.com> [ehabkost: removed test code while some issues are addressed] Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Vitaly Kuznetsov 提交于
It was found that QMP users of QEMU (e.g. libvirt) may need HV_CPUID_ENLIGHTMENT_INFO.EAX/HV_CPUID_NESTED_FEATURES.EAX information. In particular, 'hv_tlbflush' and 'hv_evmcs' enlightenments are only exposed in HV_CPUID_ENLIGHTMENT_INFO.EAX. HV_CPUID_NESTED_FEATURES.EAX is exposed for two reasons: convenience (we don't need to export it from hyperv_handle_properties() and as future-proof for Enlightened MSR-Bitmap, PV EPT invalidation and direct virtual flush features. Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20181126135958.20956-1-vkuznets@redhat.com> Reviewed-by: NRoman Kagan <rkagan@virtuozzo.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 12 12月, 2018 2 次提交
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由 Liu Jingqi 提交于
MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao <tao3.xu@intel.com> Signed-off-by: NLiu Jingqi <jingqi.liu@intel.com> Message-Id: <1541488407-17045-3-git-send-email-jingqi.liu@intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Liu Jingqi 提交于
MOVDIRI moves doubleword or quadword from register to memory through direct store which is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao <tao3.xu@intel.com> Signed-off-by: NLiu Jingqi <jingqi.liu@intel.com> Message-Id: <1541488407-17045-2-git-send-email-jingqi.liu@intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 07 11月, 2018 1 次提交
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由 Vitaly Kuznetsov 提交于
Adds a new CPU flag to enable the Enlightened VMCS KVM feature. QEMU enables KVM_CAP_HYPERV_ENLIGHTENED_VMCS and gets back the version to be advertised in lower 16 bits of CPUID.0x4000000A:EAX. Suggested-by: NLadi Prosek <lprosek@redhat.com> Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20181022165506.30332-3-vkuznets@redhat.com> Reviewed-by: NRoman Kagan <rkagan@virtuozzo.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 31 10月, 2018 1 次提交
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由 Robert Hoo 提交于
Note RSBA is specially treated -- no matter host support it or not, qemu pretends it is supported. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com> [ehabkost: removed automatic enabling of RSBA] Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 19 10月, 2018 2 次提交
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由 Roman Kagan 提交于
Certain configurations do not allow SynIC to be used in QEMU. In particular, - when hyperv_vpindex is off, SINT routes can't be used as they refer to the destination vCPU by vp_index - older KVM (which doesn't expose KVM_CAP_HYPERV_SYNIC2) zeroes out SynIC message and event pages on every msr load, breaking migration OTOH in-KVM users of SynIC -- SynIC timers -- do work in those configurations, and we shouldn't stop the guest from using them. To cover both scenarios, introduce an X86CPU property that makes CPU init code to skip creation of the SynIC object (and thus disables any SynIC use in QEMU) but keeps the KVM part of the SynIC working. The property is clear by default but is set via compat logic for older machine types. As a result, when hv_synic and a modern machine type are specified, QEMU will refuse to run unless vp_index is on and the kernel is recent enough. OTOH with an older machine type QEMU will run fine with hv_synic=on against an older kernel and/or without vp_index enabled but will disallow the in-QEMU uses of SynIC (in e.g. VMBus). Signed-off-by: NRoman Kagan <rkagan@virtuozzo.com> Message-Id: <20180921082217.29481-4-rkagan@virtuozzo.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Vitaly Kuznetsov 提交于
Hyper-V PV IPI support is merged to KVM, enable the feature in Qemu. When enabled, this allows Windows guests to send IPIs to other vCPUs with a single hypercall even when there are >64 vCPUs in the request. Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: NRoman Kagan <rkagan@virtuozzo.com> Message-Id: <20181009130853.6412-3-vkuznets@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 03 10月, 2018 3 次提交
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由 Liran Alon 提交于
While at it, also rename var to indicate it is not used only in KVM. Reviewed-by: NNikita Leshchenko <nikita.leshchenko@oracle.com> Reviewed-by: NPatrick Colp <patrick.colp@oracle.com> Signed-off-by: NLiran Alon <liran.alon@oracle.com> Message-Id: <20180914003827.124570-2-liran.alon@oracle.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
This flag will be used for KVM's nested VMX migration; the HF_GUEST_MASK name is already used in KVM, adopt it in QEMU as well. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Interrupt handling depends on various flags in env->hflags or env->hflags2, and the exact detail were not exactly replicated between x86_cpu_has_work and x86_cpu_exec_interrupt. Create a new function that extracts the highest-priority non-masked interrupt, and use it in both functions. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 24 8月, 2018 1 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 17 8月, 2018 4 次提交
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由 Robert Hoo 提交于
WBNOINVD: Write back and do not invalidate cache, enumerated by CPUID.(EAX=80000008H, ECX=0):EBX[bit 9]. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-5-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Robert Hoo 提交于
PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0): EDX[bit18]. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-4-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Robert Hoo 提交于
Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as SPEC_CTRL. At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's comment. Signed-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Robert Hoo 提交于
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdfSigned-off-by: NRobert Hoo <robert.hu@linux.intel.com> Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 30 7月, 2018 1 次提交
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由 Paolo Bonzini 提交于
MSR_SMI_COUNT started being migrated in QEMU 2.12. Do not migrate it on older machine types, or the subsection causes a load failure for guests that use SMM. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 23 7月, 2018 1 次提交
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由 Eduardo Habkost 提交于
Rename DCACHE to DATA_CACHE and ICACHE to INSTRUCTION_CACHE. This avoids conflict with Linux asm/cachectl.h macros and fixes build failure on mips hosts. Reported-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180717194010.30096-1-ehabkost@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NBabu Moger <babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 02 7月, 2018 2 次提交
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由 Jan Kiszka 提交于
This implements NPT suport for SVM by hooking into x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether we need to perform this 2nd stage translation, and how, is decided during vmrun and stored in hflags2, along with nested_cr3 and nested_pg_mode. As get_hphys performs a direct cpu_vmexit in case of NPT faults, we need retaddr in that function. To avoid changing the signature of cpu_handle_mmu_fault, this passes the value from tlb_fill to get_hphys via the CPU state. This was tested successfully via the Jailhouse hypervisor. Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Message-Id: <567473a0-6005-5843-4c73-951f476085ca@web.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Vitaly Kuznetsov 提交于
Add support for Hyper-V TLB flush which recently got added to KVM. Just like regular Hyper-V we announce HV_EX_PROCESSOR_MASKS_RECOMMENDED regardless of how many vCPUs we have. Windows is 'smart' and uses less expensive non-EX Hypercall whenever possible (when it wants to flush TLB for all vCPUs or the maximum vCPU index in the vCPU set requires flushing is less than 64). Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180610184927.19309-1-vkuznets@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 29 6月, 2018 2 次提交
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由 Michael S. Tsirkin 提交于
When guest CPU PM is enabled, and with -cpu host, expose the host CPU MWAIT leaf in the CPUID so guest can make good PM decisions. Note: the result is 100% CPU utilization reported by host as host no longer knows that the CPU is halted. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180622192148.178309-3-mst@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Jan Kiszka 提交于
It calls cpu_loop_exit in system emulation mode (and should never be called in user emulation mode). Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com> Message-Id: <6f4d44ffde55d074cbceb48309c1678600abad2f.1522769774.git.jan.kiszka@web.de> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 09 6月, 2018 1 次提交
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由 Eduardo Habkost 提交于
Always initialize CPUCaches structs with cache information, even if legacy_cache=true. Use different CPUCaches struct for CPUID[2], CPUID[4], and the AMD CPUID leaves. This will simplify a lot the logic inside cpu_x86_cpuid(). Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NBabu Moger <babu.moger@amd.com> Message-Id: <1527176614-26271-2-git-send-email-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 23 5月, 2018 1 次提交
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由 Michael S. Tsirkin 提交于
Switch to the header we imported from Linux, this allows us to drop a hack in kvm_i386.h. More code will be dropped in the next patch. Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
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- 22 5月, 2018 2 次提交
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由 Konrad Rzeszutek Wilk 提交于
"Some AMD processors only support a non-architectural means of enabling speculative store bypass disable (SSBD). To allow a simplified view of this to a guest, an architectural definition has been created through a new CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a hypervisor can virtualize the existence of this definition and provide an architectural method for using SSBD to a guest. Add the new CPUID feature, the new MSR and update the existing SSBD support to use this MSR when present." (from x86/speculation: Add virtualized speculative store bypass disable support in Linux). Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com> Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Message-Id: <20180521215424.13520-4-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Daniel P. Berrangé 提交于
New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: NDaniel P. Berrangé <berrange@redhat.com> Reviewed-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Signed-off-by: NKonrad Rzeszutek Wilk <konrad.wilk@oracle.com> Message-Id: <20180521215424.13520-2-berrange@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 15 5月, 2018 4 次提交
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由 Babu Moger 提交于
The property legacy-cache will be used to control the cache information. If user passes "-cpu legacy-cache" then older information will be displayed even if the hardware supports new information. Otherwise use the statically loaded cache definitions if available. Renamed the previous cache structures to legacy_*. If there is any change in the cache information, then it needs to be initialized in builtin_x86_defs. Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Message-Id: <20180514164156.27034-3-babu.moger@amd.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Babu Moger 提交于
Add cache information in X86CPUDefinition and CPUX86State. Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Message-Id: <20180510204148.11687-3-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Eduardo Habkost 提交于
Instead of having a collection of macros that need to be used in complex expressions to build CPUID data, define a CPUCacheInfo struct that can hold information about a given cache. Helper functions will take a CPUCacheInfo struct as input to encode CPUID leaves for a cache. This will help us ensure consistency between cache information CPUID leaves, and make the existing inconsistencies in CPUID info more visible. Signed-off-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NBabu Moger <babu.moger@amd.com> Tested-by: NGeoffrey McRae <geoff@hostfission.com> Message-Id: <20180510204148.11687-2-babu.moger@amd.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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由 Jingqi Liu 提交于
The CLDEMOTE instruction hints to hardware that the cache line that contains the linear address should be moved("demoted") from the cache(s) closest to the processor core to a level more distant from the processor core. This may accelerate subsequent accesses to the line by other cores in the same coherence domain, especially if the line was written by the core that demotes the line. Intel Snow Ridge has added new cpu feature, CLDEMOTE. The new cpu feature needs to be exposed to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: NJingqi Liu <jingqi.liu@intel.com> Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com> Reviewed-by: NEduardo Habkost <ehabkost@redhat.com> Signed-off-by: NEduardo Habkost <ehabkost@redhat.com>
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- 11 5月, 2018 1 次提交
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由 Vitaly Kuznetsov 提交于
KVM recently gained support for Hyper-V Reenlightenment MSRs which are required to make KVM-on-Hyper-V enable TSC page clocksource to its guests when INVTSC is not passed to it (and it is not passed by default in Qemu as it effectively blocks migration). Signed-off-by: NVitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20180411115036.31832-2-vkuznets@redhat.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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