- 10 6月, 2019 1 次提交
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由 Richard Henderson 提交于
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NRichard Henderson <richard.henderson@linaro.org>
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- 07 6月, 2019 36 次提交
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由 Richard Henderson 提交于
This replaces the target-specific implementations for VSEL. Signed-off-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We don't care about the other two missing base features: - S390_FEAT_DFP_PACKED_CONVERSION - S390_FEAT_GROUP_GEN13_PTFF Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Let's add it to the max model, so we can enable it. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Once we unlock S390_FEAT_VECTOR for TCG, we want linux-user to be able to make use of it. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NLaurent Vivier <laurent@vivier.eu> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can reuse float64_dcmask(). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR FP ADD. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Simulate XxC=0 and ERM=0 (current mode), so we can use the existing helper function. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
The only FP instruction we can implement without an helper. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Very similar to VECTOR FP DIVIDE. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can reuse some of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Take care of reading/indicating the 32-bit elements. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can reuse most of the infrastructure introduced for VECTOR FP CONVERT FROM FIXED 64-BIT and friends. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
We can reuse most of the infrastructure added for VECTOR FP ADD. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Provide for all three instructions all four combinations of cc bit and s bit. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
As far as I can see, there is only a tiny difference. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
1. We'll reuse op_vfa() for similar instructions later, prepare for that. 2. We'll reuse vop64_3() for other instructions later. 3. Take care of modifying the vector register only if no trap happened. - on traps, flags are not updated and no elements are modified - traps don't modify the fpc flags - without traps, all exceptions of all elements are merged 4. We'll reuse check_ieee_exc() later when we need the XxC flag. We have to check for exceptions after processing each element. Provide separate handlers for single/all element processing. We'll do the same for all applicable FP instructions. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Vector floating-point instructions will require these functions, so allow to use them from other files. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Handling is similar to data exceptions, however we can always store the VXC into the lowore and the FPC: z14 PoP, 6-20, "Vector-Exception Code" When a vector-processing exception causes a pro- gram interruption, a vector-exception code (VXC) is stored at location 147, and zeros are stored at loca- tions 144-146. The VXC is also placed in the DXC field of the floating-point-control (FPC) register if bit 45 of control register 0 is one. When bit 45 of control register 0 is zero and bit 46 of control register 0 is one, the DXC field of the FPC register and the con- tents of storage at location 147 are unpredictable. Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
The PoP (z14, 7-382) says: Doublewords to the right of the doubleword in which the highest-numbered facility bit is assigned for a model may or may not be stored. However, stack protection in certain binaries can't deal with that. "gzip" example code: f1b4: a7 08 00 03 lhi %r0,3 f1b8: b2 b0 f0 a0 stfle 160(%r15) f1bc: e3 20 f0 b2 00 90 llgc %r2,178(%r15) f1c2: c0 2b 00 00 00 01 nilf %r2,1 f1c8: b2 4f 00 10 ear %r1,%a0 f1cc: b9 14 00 22 lgfr %r2,%r2 f1d0: eb 11 00 20 00 0d sllg %r1,%r1,32 f1d6: b2 4f 00 11 ear %r1,%a1 f1da: d5 07 f0 b8 10 28 clc 184(8,%r15),40(%r1) f1e0: a7 74 00 06 jne f1ec <file_read@@base+0x1bc> f1e4: eb ef f1 30 00 04 lmg %r14,%r15,304(%r15) f1ea: 07 fe br %r14 f1ec: c0 e5 ff ff 9d 6e brasl %r14,2cc8 <__stack_chk_fail@plt> In QEMU, we currently have: max_bytes = 24 the code asks for (3 + 1) doublewords == 32 bytes. If we write 32 bytes instead of only 24, and return "2 + 1" doublewords ("one less than the number of doulewords needed to contain all of the facility bits"), the example code detects a stack corruption. In my opinion, the code is wrong. However, it seems to work fine on real machines. So let's limit storing to the minimum of the requested and the maximum doublewords. Cc: Stefan Liebler <stli@linux.ibm.com> Cc: Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
used_stfl_bytes is 0, before initialized via prepare_stfl() on the first invocation. We have to move the calculation of max_bytes after prepare_stfl(). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
CPU_DoubleU is primarily used to reinterpret between integer and floats. We don't really need this functionality. So let's just keep it simple and use an uint64_t. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
11e2bfef ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store") revealed that the vregs are not aligned to 16 bytes. Align them to 16 bytes, to avoid segfault'ing on x86. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Unfortunately, there is no easy way to avoid looping over all elements in v2. Provide specialized variants for !cc,!rt/!cc,rt/cc,!rt/cc,rt and all element types. Especially for different values of rt, the compiler might be able to optimize the code a lot. Add s390_vec_write_element(). Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Logic mostly courtesy of Richard H. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Similar to VECTOR FIND ELEMENT EQUAL. Core logic courtesy of Richard H. Add s390_vec_read_element() that can deal with element sizes. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Core logic courtesy of Richard H. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 David Hildenbrand 提交于
Complicated stuff. Provide two different helpers for CC an !CC handling. We might want to add more helpers later. zero_search() and match_index() are courtesy of Richard H. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NDavid Hildenbrand <david@redhat.com>
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由 Aleksandar Markovic 提交于
Unroll loops in helpers for MSA logic instructions for better performance. Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-5-git-send-email-aleksandar.markovic@rt-rk.com>
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由 Aleksandar Markovic 提交于
Outline places for future MSA helpers to follow the same organization as in MSA tests. Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-4-git-send-email-aleksandar.markovic@rt-rk.com>
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由 Aleksandar Markovic 提交于
Fix block-comment-related issues reported by checkpatch for file msa_helper.c. Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com>
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由 Aleksandar Markovic 提交于
Fix space-related format issues reported by checkpatch in file msa_helper.c. Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NAleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-2-git-send-email-aleksandar.markovic@rt-rk.com>
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- 03 6月, 2019 1 次提交
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由 Wanpeng Li 提交于
The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR IA32_MISC_ENABLE MWAIT bit and as userspace has control of them both, it is userspace's job to configure both bits to match on the initial setup. Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: NWanpeng Li <wanpengli@tencent.com> Message-Id: <1557813999-9175-1-git-send-email-wanpengli@tencent.com> Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 02 6月, 2019 2 次提交
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由 Mateja Marjanovic 提交于
Eliminate loops for better performance. Following MSA instructions from "UNOP" group are affected: - NLZC.<B|H|W|D> - NLOC.<B|H|W|D> - PCNT.<B|H|W|D> Following MSA instructions from "BINOP" group are affected: - ADD_A.<B|H|W|D> - ADDS_A.<B|H|W|D> - ADDS_S.<B|H|W|D> - ADDS_U.<B|H|W|D> - ADDV.<B|H|W|D> - ASUB_S.<B|H|W|D> - ASUB_U.<B|H|W|D> - AVE_S.<B|H|W|D> - AVE_U.<B|H|W|D> - AVER_S.<B|H|W|D> - AVER_U.<B|H|W|D> - BCLR.<B|H|W|D> - BNEG.<B|H|W|D> - BSET.<B|H|W|D> - CEQ.<B|H|W|D> - CLE_S.<B|H|W|D> - CLE_U.<B|H|W|D> - CLT_S.<B|H|W|D> - CLT_U.<B|H|W|D> - DIV_S.<B|H|W|D> - DIV_U.<B|H|W|D> - DOTP_S.<B|H|W|D> - DOTP_U.<B|H|W|D> - HADD_S.<B|H|W|D> - HADD_U.<B|H|W|D> - HSUB_S.<B|H|W|D> - HSUB_U.<B|H|W|D> - MAX_A.<B|H|W|D> - MAX_S.<B|H|W|D> - MAX_U.<B|H|W|D> - MIN_A.<B|H|W|D> - MIN_S.<B|H|W|D> - MIN_U.<B|H|W|D> - MOD_S.<B|H|W|D> - MOD_U.<B|H|W|D> - MUL_Q.<B|H|W|D> - MULR_Q.<B|H|W|D> - MULV.<B|H|W|D> - SLL.<B|H|W|D> - SRA.<B|H|W|D> - SRAR.<B|H|W|D> - SRL.<B|H|W|D> - SRLR.<B|H|W|D> - SUBS_S.<B|H|W|D> - SUBS_U.<B|H|W|D> - SUBSUS_U.<B|H|W|D> - SUBSUU_S.<B|H|W|D> - SUBV.<B|H|W|D> Following MSA instructions from "TEROP" group are affected: - BINSL.<B|H|W|D> - BINSR.<B|H|W|D> - DPADD_S.<B|H|W|D> - DPADD_U.<B|H|W|D> - DPSUB_S.<B|H|W|D> - DPSUB_U.<B|H|W|D> - MADD_Q.<B|H|W|D> - MADDR_Q.<B|H|W|D> - MADDV.<B|H|W|D> - MSUB_Q.<B|H|W|D> - MSUBR_Q.<B|H|W|D> - MSUBV.<B|H|W|D> Additionally, following MSA instructionas are also affected: - ILVL.<B|H|W|D> - ILVR.<B|H|W|D> - ILVEV.<B|H|W|D> - ILVOD.<B|H|W|D> - PCKEV.<B|H|W|D> - PCKOD.<B|H|W|D> Signed-off-by: NMateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NAleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1551718283-4487-2-git-send-email-mateja.marjanovic@rt-rk.com>
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由 Aleksandar Markovic 提交于
Remove several minor checkpatch warnings and errors. Signed-off-by: NAleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1556018982-3715-7-git-send-email-aleksandar.markovic@rt-rk.com>
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