1. 02 5月, 2012 5 次提交
    • P
      pseries: Fix use of global CPU state · 73f7821b
      Peter Portante 提交于
      Commit ed120055 (Implement PAPR VPA
      functions for pSeries shared processor partitions) introduced the
      deregister_dtl() function and typo "emv" as name of its argument.
      This went unnoticed because the code in that function can access the
      global variable "env" so that no build failure resulted.
      
      Fix the argument to read "env". Resolves LP#986241.
      Signed-off-by: NPeter Portante <peter.portante@redhat.com>
      Acked-by: NAndreas Färber <afaerber@suse.de>
      [agraf: fixed typo in commit message]
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      73f7821b
    • D
      pseries: Use the same interrupt swizzling for host bridges as p2p bridges · 7fb0bd34
      David Gibson 提交于
      Currently the pseries PCI code uses a somewhat strange scheme of PCI irq
      allocation - one per slot up to a maximum that's greater than the usual 4.
      This scheme more or less worked, because we were able to tell the guest the
      irq mapping in the device tree, however it's a bit odd and may break
      assumptions in the future.  Worse, the array used to construct the dev
      tree interrupt map was mis-sized, we got away with it only because it
      happened that our SPAPR_PCI_NUM_LSI value was greater than 7.
      
      This patch changes the pseries PCI code to use the same interrupt swizzling
      scheme as is standardized for PCI to PCI bridges.  This makes for better
      consistency, deals better with any devices which use multiple interrupt
      pins and will make life easier in the future when we add passthrough of
      what may be either a host bridge or a PCI to PCI bridge.  This won't break
      existing guests, because they don't assume a particular mapping scheme for
      host bridges, but just follow what we tell them in the device tree (also
      updated to match, of course).  This patch also fixes the allocation of the
      irq map.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      7fb0bd34
    • D
      pseries: Implement automatic PAPR VIO address allocation · d601fac4
      David Gibson 提交于
      PAPR virtual IO (VIO) devices require a unique, but otherwise arbitrary,
      "address" used as a token to the hypercalls which manipulate them.
      
      Currently the pseries machine code does an ok job of allocating these
      addresses when the legacy -net nic / -serial and so forth options are used
      but will fail to allocate them properly when using -device.
      
      Specifically, you can use -device if all addresses are explicitly assigned.
      Without explicit assignment, only one VIO device of each type (network,
      console, SCSI) will be assigned properly, any further ones will attempt
      to take the same address leading to a fatal error.
      
      This patch fixes the situation by adding a proper address allocator to the
      VIO "bus" code.  This is used both by -device and the legacy options and
      default devices.  Addresses can still be explicitly assigned with -device
      options if desired.
      
      This patch changes the (guest visible) numbering of VIO devices, but since
      their addresses are discovered using the device tree and already differ
      from the numbering found on existing PowerVM systems, this does not break
      compatibility.
      Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      d601fac4
    • A
      PPC: Fix up e500 cache size setting · 892c587f
      Alexander Graf 提交于
      When initializing the e500 code, we need to expose its
      cache line size for user and system mode, while the mmu
      details are only interesting for system emulation.
      
      Split the 2 switch statements apart, allowing us to #ifdef
      out the mmu parts for user mode emulation while keeping all
      cache information consistent.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      892c587f
    • B
      booke:Use MMU API for creating initial mapping for secondary cpus · 58f90f21
      Bharat Bhushan 提交于
      Initial Mapping creation for secondary CPU in SMP was missing new MMU API.
      Signed-off-by: NBharat Bhushan <bharat.bhushan@freescale.com>
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      58f90f21
  2. 01 5月, 2012 17 次提交
  3. 30 4月, 2012 13 次提交
  4. 29 4月, 2012 4 次提交
  5. 28 4月, 2012 1 次提交