1. 18 4月, 2010 3 次提交
  2. 12 4月, 2010 1 次提交
  3. 09 4月, 2010 1 次提交
  4. 26 2月, 2010 1 次提交
  5. 20 2月, 2010 1 次提交
  6. 09 1月, 2010 1 次提交
  7. 24 9月, 2009 1 次提交
    • I
      sparc64-8bit-asi · 01b5d4e5
      Igor V. Kovalenko 提交于
      Sparc64 alternate space load/store helpers expect 8 bit ASI value,
      while wrasi implementation sign-extends ASI operand causing
      for example 0x80 to appear as 0xFFFFFF80. Resulting value falls
      out of switch in helpers and causes obscure load/store faults.
      
      - correct wrasi by masking lower 8 bits of xor result
      - use lower 8 bits of ASI register in helpers
      Signed-off-by: NIgor V. Kovalenko <igor.v.kovalenko@gmail.com>
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      01b5d4e5
  8. 12 9月, 2009 1 次提交
    • B
      Fix sys-queue.h conflict for good · 72cf2d4f
      Blue Swirl 提交于
      Problem: Our file sys-queue.h is a copy of the BSD file, but there are
      some additions and it's not entirely compatible. Because of that, there have
      been conflicts with system headers on BSD systems. Some hacks have been
      introduced in the commits 15cc9235,
      f40d7537,
      96555a96 and
      3990d09a but the fixes were fragile.
      
      Solution: Avoid the conflict entirely by renaming the functions and the
      file. Revert the previous hacks.
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      72cf2d4f
  9. 22 8月, 2009 1 次提交
  10. 16 8月, 2009 1 次提交
  11. 05 8月, 2009 1 次提交
    • I
      Sparc64: replace tsptr with helper routine · 8194f35a
      Igor Kovalenko 提交于
      tl and tsptr of members sparc64 cpu state must be changed
      simultaneously to keep trap state window in sync with current
      trap level. Currently translation of store to tl does not change
      tsptr, which leads to corrupt trap state on corresponding
      trap level.
      
      This patch removes tsptr from sparc64 cpu state and replaces
      all uses with call to helper routine.
      
      Changes v0->v1:
      - reimplemented helper routine with tcg generator
      - on cpu reset trap type and pstate are populated with power-on reset
      values, including tl=maxtl
      
      Signed-off-by: igor.v.kovalenko@gmail.com
      Signed-off-by: NBlue Swirl <blauwirbel@gmail.com>
      8194f35a
  12. 31 7月, 2009 1 次提交
    • I
      sparc64 flush pending conditional evaluations before exposing cpu state · 14ed7adc
      Igor Kovalenko 提交于
      If translation block is interrupted by e.g. mmu exception
      we need to compute conditional flags for inclusion into
      saved cpu state. Otherwise after return from trap
      conditional instructions would use stale psr/xcc data.
      
      Signed-off-by: igor.v.kovalenko@gmail.com
      
      --
      Kind regards,
      Igor V. Kovalenko
      14ed7adc
  13. 17 7月, 2009 1 次提交
  14. 06 6月, 2009 1 次提交
  15. 10 5月, 2009 9 次提交
  16. 04 5月, 2009 2 次提交
  17. 03 5月, 2009 3 次提交
  18. 06 4月, 2009 1 次提交
  19. 17 3月, 2009 1 次提交
  20. 16 1月, 2009 2 次提交
  21. 05 1月, 2009 1 次提交
  22. 26 11月, 2008 1 次提交
  23. 19 11月, 2008 1 次提交
    • A
      Refactor and enhance break/watchpoint API (Jan Kiszka) · a1d1bb31
      aliguori 提交于
      This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
      succeeding enhancements this series comes with.
      
      First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
      to dynamically allocated data structures that are kept in linked lists.
      This also allows to return a stable reference to the related objects,
      required for later introduced x86 debug register support.
      
      Breakpoints and watchpoints are stored with their full information set
      and an additional flag field that makes them easily extensible for use
      beyond pure guest debugging.
      Signed-off-by: NJan Kiszka <jan.kiszka@siemens.com>
      Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
      
      
      
      git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
      a1d1bb31
  24. 17 11月, 2008 1 次提交
  25. 10 11月, 2008 2 次提交