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  1. 05 3月, 2014 8 次提交
  3. 11 10月, 2013 1 次提交
  5. 27 4月, 2013 2 次提交
  7. 22 3月, 2013 1 次提交
    • D
      target-ppc: Remove vestigial PowerPC 620 support · 9baea4a3
      由 David Gibson 提交于 
      The PowerPC 620 was the very first 64-bit PowerPC implementation, but
hardly anyone ever actually used the chips.  qemu notionally supports the
620, but since we don't actually have code to implement the segment table,
the support is broken (quite likely in other ways too).

This patch, therefore, removes all remaining pieces of 620 support, to
stop it cluttering up the platforms we actually care about.  This includes
removing support for the ASR register, used only on segment table based
machines.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      9baea4a3
  9. 24 2月, 2013 1 次提交
  11. 01 2月, 2013 1 次提交
    • A
      PPC: Unify dcbzl code path · 8e33944f
      由 Alexander Graf 提交于 
      The bit that makes a dcbz instruction a dcbzl instruction was declared as
reserved in ppc32 ISAs. However, hardware simply ignores the bit, making
code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4.

Thus, mark the bit as unreserved so that we properly emulate a simple dcbz
in case we're running on non-G5s.

While at it, also refactor the code to check the 970 special case during
runtime. This way we don't need to differenciate between a 970 dcbz and
any other dcbz anymore. We also allow for future improvements to add e500mc
dcbz handling.
Reported-by: NAmadeusz Sławiński <amade@asmblr.net>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      8e33944f
  13. 08 1月, 2013 1 次提交
    • A
      PPC: Bring EPR support closer to reality · 68c2dd70
      由 Alexander Graf 提交于 
      We already used to support the external proxy facility of FSL MPICs,
but only implemented it halfway correctly.

This patch adds support for

  * dynamic enablement of the EPR facility
  * interrupt acknowledgement only when the interrupt is delivered

This way the implementation now is closer to real hardware.
Signed-off-by: NAlexander Graf <agraf@suse.de>
      68c2dd70
  15. 19 12月, 2012 1 次提交
  17. 28 10月, 2012 1 次提交
  19. 24 6月, 2012 8 次提交
  21. 02 2月, 2012 3 次提交
  23. 03 6月, 2011 1 次提交
  25. 12 5月, 2011 1 次提交
    • A
      PPC: Implement e500 (FSL) MMU · 01662f3e
      由 Alexander Graf 提交于 
      Most of the code to support e500 style MMUs is already in place, but
we're missing on some of the special TLB0-TLB1 handling code and slightly
different TLB modification.

This patch adds support for the FSL style MMU.
Signed-off-by: NAlexander Graf <agraf@suse.de>
      01662f3e
  27. 02 4月, 2011 4 次提交
    • D
      Correct ppc popcntb logic, implement popcntw and popcntd · eaabeef2
      由 David Gibson 提交于 
      qemu already includes support for the popcntb instruction introduced
in POWER5 (although it doesn't actually allow you to choose POWER5).

However, the logic is slightly incorrect: it will generate results
truncated to 32-bits when the CPU is in 32-bit mode.  This is not
normal for powerpc - generally arithmetic instructions on a 64-bit
powerpc cpu will generate full 64 bit results, it's just that only the
low 32 bits will be significant for condition codes.

This patch corrects this nit, which actually simplifies the code slightly.

In addition, this patch implements the popcntw and popcntd
instructions added in POWER7, in preparation for allowing POWER7 as an
emulated CPU.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      eaabeef2
    • D
      Implement missing parts of the logic for the POWER PURR · 3a7f009a
      由 David Gibson 提交于 
      The PURR (Processor Utilization Resource Register) is a register found
on recent POWER CPUs.  The guts of implementing it at least enough to
get by are already present in qemu, however some of the helper
functions needed to actually wire it up are missing.

This patch adds the necessary glue, so that the PURR can be wired up
when we implement newer POWER CPU targets which include it.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      3a7f009a
    • D
      Implement PowerPC slbmfee and slbmfev instructions · efdef95f
      由 David Gibson 提交于 
      For a 64-bit PowerPC target, qemu correctly implements translation
through the segment lookaside buffer.  Likewise it supports the
slbmte instruction which is used to load entries into the SLB.

However, it does not emulate the slbmfee and slbmfev instructions
which read SLB entries back into registers.  Because these are
only occasionally used in guests (mostly for debugging) we get
away with it.

However, given the recent SLB cleanups, it becomes quite easy to
implement these, and thereby allow, amongst other things, a guest
Linux to use xmon's command to dump the SLB.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      efdef95f
    • D
      Clean up PowerPC SLB handling code · 81762d6d
      由 David Gibson 提交于 
      Currently the SLB information when emulating a PowerPC 970 is
storeed in a structure with the unhelpfully named fields 'tmp'
and 'tmp64'.  While the layout in these fields does match the
description of the SLB in the architecture document, it is not
convenient either for looking up the SLB, or for emulating the
slbmte instruction.

This patch, therefore, reorganizes the SLB entry structure to be
divided in the the "ESID related" and "VSID related" fields as
they are divided in instructions accessing the SLB.

In addition to making the code smaller and more readable, this will
make it easier to implement for the 1TB segments used in more
recent PowerPC chips.
Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
Signed-off-by: NAlexander Graf <agraf@suse.de>
      81762d6d
  29. 14 7月, 2010 1 次提交
  31. 16 6月, 2010 1 次提交
    • R
      tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts. · 2bece2c8
      由 Richard Henderson 提交于 
      Some hosts (amd64, ia64) have an ABI that ignores the high bits
of the 64-bit register when passing 32-bit arguments.  Others
require the value to be properly sign-extended for the type.
I.e. "int32_t" must be sign-extended and "uint32_t" must be
zero-extended to 64-bits.

To effect this, extend the "sizemask" parameter to tcg_gen_callN
to include the signedness of the type of each parameter.  If the
tcg target requires it, extend each 32-bit argument into a 64-bit
temp and pass that to the function call.

This ABI feature is required by sparc64, ppc64 and s390x.
Signed-off-by: NRichard Henderson <rth@twiddle.net>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>
      2bece2c8
  33. 07 2月, 2010 1 次提交
  35. 21 12月, 2009 1 次提交
  37. 02 10月, 2009 2 次提交