- 24 4月, 2014 1 次提交
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由 Peter Maydell 提交于
trivial patches for 2014-04-18 # gpg: Signature made Fri 18 Apr 2014 07:36:15 BST using RSA key ID A4C3D7DB # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" # gpg: aka "Michael Tokarev <mjt@corpit.ru>" # gpg: aka "Michael Tokarev <mjt@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 6F67 E18E 7C91 C5B1 5514 66A7 BEE5 9D74 A4C3 D7DB * remotes/mjt/tags/trivial-patches-2014-04-18: Fix grammar in comment doc: grammify "allows to" configure: Remove redundant message for -Werror scripts: add sample model file for Coverity Scan xbzrle.c: Avoid undefined behaviour with signed arithmetic int128.h: Avoid undefined behaviours involving signed arithmetic hw/ide/ahci.c: Avoid shift left into sign bit net: Report error when device / hub combo is not found. configure: Fix indentation of help for --enable/disable-debug-info qga: trivial fix for unclear documentation of guest-set-time vl: Report accelerator not supported for target more nicely Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 4月, 2014 39 次提交
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由 Stefan Weil 提交于
Signed-off-by: NStefan Weil <sw@weilnetz.de> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Michael Tokarev 提交于
English language grammar does not allow usage of the word "allows" directly followed by an infinitive, declaring constructs like "something allows to do somestuff" un-grammatical. Often it is possible to just insert "one" between "allows" and "to" to make the construct grammatical, but usually it is better to re-phrase the statement. This patch tries to fix 4 examples of "allows to" usage in qemu doc, but does not address comments in the code with similar constructs. It also adds missing "the" in the same line. Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Stefan Weil 提交于
The compiler flag -Werror is printed (or not printed) as any other compiler flag which is part of QEMU_CFLAGS. Therefore an extra output line for -Werror is redundant and can be removed. Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Paolo Bonzini 提交于
This is the model file that is being used for the QEMU project's scans on scan.coverity.com. It fixed about 30 false positives (10% of the total) and exposed about 60 new memory leaks. The file is not automatically used; changes to it must be propagated to the website manually by an admin (right now Markus, Peter and me are admins). Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com> Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Peter Maydell 提交于
Use unsigned types for doing bitwise arithmetic in the xzbrle calculations, to avoid undefined behaviour: xbzrle.c:99:49: runtime error: left shift of 72340172838076673 by 7 places cannot be represented in type 'long' Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Peter Maydell 提交于
Add casts when we're performing arithmetic on the .hi parts of an Int128, to avoid undefined behaviour. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Peter Maydell 提交于
Add U suffix to avoid shifting left into the sign bit, which is undefined behaviour. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Hani Benhabiles 提交于
Also convert nearby monitor_printf() call to error_report(). Signed-off-by: NHani Benhabiles <hani@linux.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Peter Maydell 提交于
The help text for the --enable-debug-info and --disable-debug-info command line options was misindented: delete the stray extra space and bring it in to line with everything else. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Amos Kong 提交于
We mixed the use of "guest time", "system time", "hardware time", "RTC" in documentation, it's unclear. This patch just added two remarks of RTC and replace two "guest time" by "guest's system time". Signed-off-by: NAmos Kong <akong@redhat.com> Reviewed-by: NMichal Privoznik <mprivozn@redhat.com> Reviewed-by: NEric Blake <eblake@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Chen Gang 提交于
When you ask for an accelerator not supported for your target, you get a bogus "accelerator does not exist" message: $ qemu-system-arm -machine none,accel=kvm KVM not supported for this target "kvm" accelerator does not exist. No accelerator found! Suppress it. Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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由 Peter Maydell 提交于
target-arm queue: * AArch64 system mode support; this is all the CPU emulation code but not the virt board support * cadence_ttc match register bugfix * Allwinner A10 PIC, PIT and ethernet fixes [with update to avoid duplicate typedef] * zynq-slcr rewrite * cadence_gem bugfix * fix for SMLALD/SMLSLD insn in A32 * fix for SQXTUN in A64 # gpg: Signature made Thu 17 Apr 2014 21:35:57 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140417-1: (51 commits) target-arm: A64: fix unallocated test of scalar SQXTUN arm: translate.c: Fix smlald Instruction net: cadence_gem: Make phy respond to broadcast misc: zynq_slcr: Make DB_PRINTs always compile misc: zynq_slcr: Convert SBD::init to object init misc: zynq-slcr: Rewrite allwinner-emac: update irq status after writes to interrupt registers allwinner-emac: set autonegotiation complete bit on link up allwinner-a10-pit: implement prescaler and source selection allwinner-a10-pit: use level triggered interrupts allwinner-a10-pit: avoid generation of spurious interrupts allwinner-a10-pic: fix behaviour of pending register allwinner-a10-pic: set vector address when an interrupt is pending timer: cadence_ttc: Fix match register write logic target-arm/gdbstub64.c: remove useless 'break' statement. target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc target-arm: Make Cortex-A15 CBAR read-only target-arm: Implement CBAR for Cortex-A57 target-arm: Implement Cortex-A57 implementation-defined system registers ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
The test for the U bit was incorrectly inverted in the scalar case of SQXTUN. This doesn't affect the vector case as the U bit is used to select XTN(2). Reported-by: NHao Liu <hao.liu@arm.com> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NClaudio Fontana <claudio.fontana@huawei.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
The smlald (and probably smlsld) instruction was doing incorrect sign extensions of the operands amongst 64bit result calculation. The instruction psuedo-code is: operand2 = if m_swap then ROR(R[m],16) else R[m]; product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>); product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>); result = product1 + product2 + SInt(R[dHi]:R[dLo]); R[dHi] = result<63:32>; R[dLo] = result<31:0>; The result calculation should be done in 64 bit arithmetic, and hence product1 and product2 should be sign extended to 64b before calculation. The current implementation was adding product1 and product2 together then sign-extending the intermediate result leading to false negatives. E.G. if product1 = product2 = 0x4000000, their sum = 0x80000000, which will be incorrectly interpreted as -ve on sign extension. We fix by doing the 64b extensions on both product1 and product2 before any addition/subtraction happens. We also fix where we were possibly incorrectly setting the Q saturation flag for SMLSLD, which the ARM ARM specifically says is not set. Reported-by: NChristina Smith <christina.smith@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 2cddb6f5a15be4ab8d2160f3499d128ae93d304d.1397704570.git.peter.crosthwaite@xilinx.com Cc: qemu-stable@nongnu.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Phys must respond to address 0 by specification. Implement. Signed-off-by: NNathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 6f4d53b04ddbfb19895bfb61a595e69f1c08859a.1396594056.git.peter.crosthwaite@xilinx.com Reviewed-by: NBeniamino Galvani <b.galvani@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Change the DB_PRINT macro over to a regular if() rather than conditional compilation to give constant compile testing of formats. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 942477847353c5cff5f45a228cc88c633dc012f3.1396503037.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
To bring it up to date with styling guidelines. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2e837af80a18216c21e73241032e048f39d78b99.1396503037.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Near total rewrite of this device model. It is stylistically obsolete, has numerous coverity fails and is not up to date with latest Xilinx documentation. Fix. The registers are flattened into a single array. This greatly simplifies the MMIO accessor functions. We take the oppurtunity to update the register Macro definitions to match the latest TRM. Xilinx has de-documented some regs hence there are some straight deletions. We only do this however in the case or a stock read-as-written reset-zero register. Non-zero resets are always preserved. New register definitions are added as needed. This all comes with a VMSD version break as the union layout from before was a bit strange and we are better off without it. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3aa016167b352ed224666909217137285fd3351d.1396503037.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
The irq line status must be updated after writes to the INT_CTL and INT_STA registers. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-8-git-send-email-b.galvani@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-7-git-send-email-b.galvani@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
This implements the prescaler and source fields of the timer control register. The source for each timer can be selected among 4 clock inputs whose frequencies are set through model properties. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-6-git-send-email-b.galvani@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-5-git-send-email-b.galvani@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
The model was generating interrupts for all enabled timers after the expiration of one of them. Avoid this by passing explicitly the timer index to the callback function. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NLi Guang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-4-git-send-email-b.galvani@gmail.com [PMM: avoid duplicate typedef of AwA10PITState] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
The pending register is read-only and the value returned upon a read reflects the state of irq input pins (interrupts are level triggered). This patch implements such behaviour. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NLi Guang <lig.fnst@cn.fujitsu.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1395771730-16882-3-git-send-email-b.galvani@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Beniamino Galvani 提交于
This patch implements proper updating of the vector register which should hold, according to the A10 user manual, the vector address for the interrupt currently active on the CPU IRQ input. Interrupt priority is not implemented at the moment and thus the first pending interrupt is returned. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NLi Guang <lig.fnst@cn.fujitsu.com> Message-id: 1395771730-16882-2-git-send-email-b.galvani@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
This switch logic should not fall through. Fix. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 74147b4c017c904364955cc73107f90e6ac8ba74.1396326389.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Chen Gang 提交于
Clean up useless 'break' statement after 'return' statement. Signed-off-by: NChen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
For system mode, we may have a 64 bit CPU which is currently executing in AArch32 state; if we're dumping CPU state to the logs we should therefore show the correct state for the current execution state, rather than hardwiring it based on the type of the CPU. For consistency with how we handle translation, we leave the 32 bit dump function as the default, and have it hand off control to the 64 bit dump code if we're in AArch64 mode. Reported-by: NRob Herring <rob.herring@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The AArch64 implementation of the set_pc method needs to be updated to handle the possibility that the CPU is in AArch32 mode; otherwise there are weird crashes when doing interprocessing in system emulation mode when an interrupt occurs and we fail to resynchronize the 32-bit PC with the TB we need to execute next. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The Cortex-A15's CBAR register is actually read-only (unlike that of the Cortex-A9). Correct our model to match the hardware. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The Cortex-A57, like most of the other ARM cores, has a CBAR register which defines the base address of the per-CPU peripherals. However it has a 64-bit view as well as a 32-bit view; expand the QOM reset-cbar property from UINT32 to UINT64 so this can be specified, and implement the 32-bit and 64-bit views of a 64-bit CBAR. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement a subset of the Cortex-A57's implementation defined system registers. We provide RAZ/WI or reads-as-constant/writes-ignored implementations of the various control and syndrome reigsters. We do not implement registers which provide direct access to and manipulation of the L1 cache, since QEMU doesn't implement caches. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 RVBAR register, which indicates the reset address. Since the reset address is implementation defined and usually configurable by setting config signals in hardware, we also provide a QOM property so it can be set at board level if necessary. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the AArch64 address translation operations. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the auxiliary fault status registers AFSR0_EL1 and AFSR1_EL1. These are present on v7 and later, and have IMPDEF behaviour; we choose to RAZ/WI for all cores. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Many of the reginfo definitions in cp_reginfo[] use CP_ANY wildcards. This is for a combination of reasons: * early ARM implementations really did underdecode * earlier versions of QEMU underdecoded and we can't tighten this up because we don't know if guests really require this or not * implementation convenience For ARMv8 the architecture has tightened things up and system and coprocessor registers are always specifically decoded. We take advantage of this opportunity for a clean break by restricting our CP_ANY wildcarded reginfo to pre-v8 CPUs, and providing specifically decoded versions where necessary for v8 CPUs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
In ARMv8 the 32 bit coprocessor ID register space is tidied up to remove the wildcarded aliases of the MIDR and the RAZ behaviour for the unassigned space where crm = 3..7. Make sure we don't expose thes wildcards for v8 cores. This means we need to have a specific implementation for REVIDR, an IMPDEF register which may be the same as the MIDR (and which we always implement as such). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The AArch64 usermode 'any' CPU type was accidentally specified with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since ARMv8 removes Thumb2EE completely. Since we never implemented Thumb2EE anyway having the feature bit set was fairly harmless for user-mode, but the correct thing is to not set it at all. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the ISR_EL1 register. This is actually present in ARMv7 as well but was previously unimplemented. It is a read-only register that indicates whether interrupts are currently pending. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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