- 20 6月, 2012 36 次提交
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由 Peter Maydell 提交于
There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the final ID registers to the new cp15 scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 cache ID registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=0 crm={1,2} features registers to the new cp reg framework. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=1 registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the MMU fault status and MPU access permission cp15 registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the (dummy) generic timer cp15 implementation. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert TLS registers to the new cp15 framework Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the coprocessor access functions for the pxa2xx PIC to the arm_cp_reginfo scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the new arm_cp_reginfo scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the PXA2xx cp14 perf registers from old-style coprocessor hooks to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Crístian Viana 提交于
QEMU exposes its version to the guest's hardware and in some cases that is wrong (e.g. Windows prints messages about driver updates when you switch the QEMU version). There is a new field now on the struct QEmuMachine, hw_version, which may contain the version that the specific machine should report. If that field is set, then that machine will report that version to the guest. Signed-off-by: NCrístian Viana <vianac@linux.vnet.ibm.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Gleb Natapov 提交于
This patch adds two things. First it allows QEMU to distinguish between regular powerdown and S4 powerdown. Later separate QMP notification will be added for S4 powerdown. Second it allows S3/S4 states to be disabled from QEMU command line. Some guests known to be broken with regards to power management, but allow to use it anyway. Using new properties management will be able to disable S3/S4 for such guests. Supported system state are passed to a firmware using new fw_cfg file. The file contains 6 byte array. Each byte represents one system state. If byte at offset X has its MSB set it means that system state X is supported and to enter it guest should use the value from lowest 3 bits. Signed-off-by: NGleb Natapov <gleb@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Anthony Liguori 提交于
I think I understand enough of what's going on in these rules to ensure this is right. But I could certainly use a second or third opinion... Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Avi Kivity 提交于
Fedora 17's toolchain wants optimization enabled for _FORTIFY_SOURCE; so disable _FORTIFY_SOURCE when debugging. Signed-off-by: NAvi Kivity <avi@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 18 6月, 2012 4 次提交
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由 Anthony Liguori 提交于
* afaerber-or/qom-next-2: (22 commits) qom: Push error reporting to object_property_find() qdev: Remove qdev_prop_exists() qbus: Initialize in standard way qbus: Make child devices links qdev: Connect busses with their parent devices qdev: Convert busses to QEMU Object Model qdev: Move SysBus initialization to sysbus.c qdev: Use wrapper for qdev_get_path qdev: Remove qdev_prop_set_defaults qdev: Clean up global properties qdev: Move bus properties to abstract superclasses qdev: Move bus properties to a separate global qdev: Push "type" property up to Object arm_l2x0: Rename "type" property to "cache-type" m48t59: Rename "type" property to "model" qom: Assert that public types have a non-NULL parent field qom: Drop type_register_static_alias() macro qom: Make Object a type qom: Add class_base_init qom: Add object_child_foreach() ...
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由 Anthony Liguori 提交于
* qmp/queue/qmp: build: install qmp-commands.txt Add rate limiting of RTC_CHANGE, BALLOON_CHANGE & WATCHDOG events Add event notification for guest balloon changes Fix some more license versions (GPL2+ instead of GPL2) monitor: Fix memory leak with readline completion qmp: do not include monitor.h from qapi-types-core.h qmp: include monitor.h when needed kvm: add missing include files
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由 Anthony Liguori 提交于
* kwolf/for-anthony: (39 commits) qemu-iotests: add 036 autoclear feature bit test qemu-iotests: add qcow2.py set-feature-bit command fdc-test: introduced qtest read_without_media fdc: fix implied seek while there is no media in drive qcow2: fix autoclear image header update xen: Don't peek behind the BlockDriverState abstraction xen: Don't change -drive if=xen device name during machine init block: Replace bdrv_get_format() by bdrv_get_format_name() qemu-img: document qed format on qemu-img man page qemu-iotests: COW with many AIO requests on the same cluster qemu-iotests: Some backing file COW tests qcow2: Fix avail_sectors in cluster allocation code qcow2: Simplify calculation for COW area at the end qcow2: always operate caches in writeback mode ide: support enable/disable write cache block: always open drivers in writeback mode block: add bdrv_set_enable_write_cache block: copy enable_write_cache in bdrv_append savevm: flush after saving vm state block: flush in writethrough mode after writes ...
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由 Anthony Liguori 提交于
* mst/tags/for_anthony: pci_bridge_dev: fix error path in pci_bridge_dev_initfn() qdev: release parent properties on dc->init failure msi: Use msi/msix_present more consistently msi: Invoke msi/msix_write_config from PCI core msi: Guard msi/msix_write_config with msi_present msi: Invoke msi/msix_reset from PCI core msi: Guard msi_reset with msi_present ahci: Clean up reset functions intel-hda: Fix reset of MSI function ahci: Fix reset of MSI function rtl8139: honor RxOverflow flag in can_receive method shpc: unparent device before free
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