- 12 5月, 2015 1 次提交
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由 Fabian Aggeler 提交于
Create the outbound FIQ lines from the GIC to the CPUs; these are used if the GIC has security extensions or grouping support. Signed-off-by: NFabian Aggeler <aggelerf@ethz.ch> Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-2-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-2-git-send-email-greg.bellows@linaro.org [PMM: added FIQ lines to kvm-arm-gic so its interface is the same; tweaked commit message] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 19 3月, 2015 1 次提交
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由 Stefan Weil 提交于
Sparse report: hw/display/vga.c:2000:5: warning: returning void-valued expression hw/intc/arm_gic.c:707:9: warning: returning void-valued expression hw/intc/etraxfs_pic.c:138:9: warning: returning void-valued expression hw/nvram/fw_cfg.c:475:5: warning: returning void-valued expression hw/timer/a9gtimer.c:124:5: warning: returning void-valued expression hw/tpm/tpm_tis.c:794:5: warning: returning void-valued expression hw/usb/hcd-musb.c:558:9: warning: returning void-valued expression hw/usb/hcd-musb.c:776:13: warning: returning void-valued expression hw/usb/hcd-musb.c:867:5: warning: returning void-valued expression hw/usb/hcd-musb.c:932:5: warning: returning void-valued expression include/qom/cpu.h:584:5: warning: returning void-valued expression monitor.c:4686:13: warning: returning void-valued expression monitor.c:4690:13: warning: returning void-valued expression Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: NStefan Weil <sw@weilnetz.de> Signed-off-by: NMichael Tokarev <mjt@tls.msk.ru>
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- 24 10月, 2014 1 次提交
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由 KONRAD Frederic 提交于
This removes num_irq parameter from gic_init_irqs_and_distributor as it is not used. Signed-off-by: NKONRAD Frederic <fred.konrad@greensocs.com> Message-id: 1412859651-15060-1-git-send-email-fred.konrad@greensocs.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 8月, 2014 4 次提交
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由 Sergey Fedorov 提交于
Take IRQ target mask into account when determining the highest priority pending interrupt. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> Acked-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1407947471-26981-1-git-send-email-serge.fdrv@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Adam Lackorzynski 提交于
Only SGIs must be WI, done by forcing them to their default (edge-triggered). Acked-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NAdam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-4-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Adam Lackorzynski 提交于
Setting the model is only available in pre-v1 GIC models. Acked-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NAdam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-3-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Adam Lackorzynski 提交于
The GICD_ICFGR register covers 4 interrupts per byte. Acked-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NAdam Lackorzynski <adam@os.inf.tu-dresden.de> Message-id: 1408372255-12358-2-git-send-email-adam@os.inf.tu-dresden.de Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 06 5月, 2014 1 次提交
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由 Markus Armbruster 提交于
Using error_is_set(ERRP) to find out whether a function failed is either wrong, fragile, or unnecessarily opaque. It's wrong when ERRP may be null, because errors go undetected when it is. It's fragile when proving ERRP non-null involves a non-local argument. Else, it's unnecessarily opaque (see commit 84d18f06). I guess the error_is_set(errp) in the DeviceClass realize() methods are merely fragile right now, because I can't find a call chain that passes a null errp argument. Make the code more robust and more obviously correct: receive the error in a local variable, then propagate it through the parameter. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Acked-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 20 2月, 2014 1 次提交
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由 Peter Maydell 提交于
Commit 40d22500 accidentally changed the behaviour of gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs, so this meant we hit an assertion: gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed. Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NChristoffer Dall <christoffer.dall@linaro.org>
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- 08 2月, 2014 4 次提交
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由 Christoffer Dall 提交于
The GICC_APRn registers are not currently supported by the ARM GIC v2.0 emulation. This patch adds the missing state. Note that we also change the number of APRs to use a define GIC_NR_APRS based on the maximum number of preemption levels. This patch also adds RAZ/WI accessors for the four registers on the emulated CPU interface. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
Right now the arm gic emulation doesn't keep track of the source of an SGI (which apparently Linux guests don't use, or they're fine with assuming CPU 0 always). Add the necessary matrix on the GICState structure and maintain the data when setting and clearing the pending state of an IRQ and make the state visible to the guest. Note that we always choose to present the source as the lowest-numbered CPU in case multiple cores have signalled the same SGI number to a core on the system. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
The existing implementation of the pending behavior in gic_set_irq, gic_complete_irq, and the distributor pending set/clear registers does not follow the semantics of the GICv2.0 specs, but may implement the 11MPCore support. Therefore, maintain the existing semantics for 11MPCore and v7M NVIC and change the behavior to be in accordance with the GICv2.0 specs for "generic implementations" (s->revision == 1 || s->revision == 2). Generic implementations distinguish between setting a level-triggered interrupt pending through writes to the GICD_ISPENDR and when hardware raises the interrupt line. Writing to the GICD_ICPENDR will not cause the interrupt to become non-pending if the line is still active, and conversely, if the line is deactivated but the interrupt is marked as pending through a write to GICD_ISPENDR, the interrupt remains pending. Handle this situation in the GIC_TEST_PENDING (which now becomes a static inline named gic_test_pending) and let the 'pending' field correspond only to the latched state of the D-flip flop in the GICv2.0 specs Figure 4-10. The following changes are added: gic_test_pending: Make this a static inline and split out the 11MPCore from the generic behavior. For the generic behavior, consider interrupts pending if: ((s->irq_state[irq].pending & (cm) != 0) || (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm)) gic_set_irq: Split out the 11MPCore from the generic behavior. For the generic behavior, always GIC_SET_LEVEL() on positive level, but only GIC_SET_PENDING for edge-triggered interrupts and always simply GIC_CLEAR_LEVEL() on negative level. gic_complete_irq: Only resample the line for line-triggered interrupts on an 11MPCore. Generic implementations will sample the line directly in gic_test_pending(). Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 31 1月, 2014 2 次提交
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由 Christoffer Dall 提交于
Fix two bugs that would allow changing the state of SGIs through the ICPENDR and ISPENDRs. Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
Instead of hardcoding 16 various places in the code, use a define to make it more clear what is going on. Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 09 1月, 2014 2 次提交
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由 Christoffer Dall 提交于
To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 08 1月, 2014 2 次提交
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由 Christoffer Dall 提交于
To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this function to set the priority of interrupts. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-3-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Christoffer Dall 提交于
TRIGGER can really mean mean anything (e.g. was it triggered, is it level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to make the code comprehensible without looking up the data structure. Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org> Message-id: 1387606179-22709-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 12月, 2013 2 次提交
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由 Markus Armbruster 提交于
device_add plugs devices into suitable bus. For "real" buses, that actually connects the device. For sysbus, the connections need to be made separately, and device_add can't do that. The device would be left unconnected, and could not possibly work. Quite a few, but not all sysbus devices already set cannot_instantiate_with_device_add_yet in their class init function. Set it in their abstract base's class init function sysbus_device_class_init(), and remove the now redundant assignments from device class init functions. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NMarcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Markus Armbruster 提交于
In an ideal world, machines can be built by wiring devices together with configuration, not code. Unfortunately, that's not the world we live in right now. We still have quite a few devices that need to be wired up by code. If you try to device_add such a device, it'll fail in sometimes mysterious ways. If you're lucky, you get an unmysterious immediate crash. To protect users from such badness, DeviceClass member no_user used to make device models unavailable with -device / device_add, but that regressed in commit 18b6dade. The device model is still omitted from help, but is available anyway. Attempts to fix the regression have been rejected with the argument that the purpose of no_user isn't clear, and it's prone to misuse. This commit clarifies no_user's purpose. Anthony suggested to rename it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which I shorten somewhat to keep checkpatch happy. While there, make it bool. Every use of cannot_instantiate_with_device_add_yet gets a FIXME comment asking for rationale. The next few commits will clean them all up, either by providing a rationale, or by getting rid of the use. With that done, the regression fix is hopefully acceptable. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NMarcel Apfelbaum <marcel.a@redhat.com> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 30 7月, 2013 1 次提交
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由 Andreas Färber 提交于
Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 10 7月, 2013 2 次提交
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由 Andreas Färber 提交于
Since current_cpu is CPUState it no longer needs CPUArchState. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Andreas Färber 提交于
Move it to qom/cpu.h. Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 04 7月, 2013 2 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 09 4月, 2013 2 次提交
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由 Paolo Bonzini 提交于
Many headers are used only in a single directory. These can be kept in hw/. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 05 3月, 2013 1 次提交
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由 Peter Maydell 提交于
Convert the ARM GIC classes to use init/realize rather than SysBusDevice::init. (We have to do them all in one patch to avoid unconverted subclasses calling a nonexistent SysBusDevice init function in the base class and crashing.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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- 01 3月, 2013 1 次提交
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由 Paolo Bonzini 提交于
Done with this script: cd hw for i in `find . -name '*.h' | sed 's/^..//'`; do echo '\,^#.*include.*["<]'$i'[">], s,'$i',hw/&,' done | sed -i -f - `find . -type f` This is so that paths remain valid as files are moved. Instead, files in hw/dataplane are referenced with the relative path. We know they are not going to move to include/, and they are the only include files that are in subdirectories _and_ move. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 15 1月, 2013 1 次提交
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由 Andreas Färber 提交于
Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: NAndreas Färber <afaerber@suse.de>
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- 11 1月, 2013 1 次提交
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由 Andreas Färber 提交于
Since 39bffca2 (qdev: register all types natively through QEMU Object Model), TypeInfo as used in the common, non-iterative pattern is no longer amended with information and should therefore be const. Fix the documented QOM examples: sed -i 's/static TypeInfo/static const TypeInfo/g' include/qom/object.h Since frequently the wrong examples are being copied by contributors of new devices, fix all types in the tree: sed -i 's/^static TypeInfo/static const TypeInfo/g' */*.c sed -i 's/^static TypeInfo/static const TypeInfo/g' */*/*.c This also avoids to piggy-back these changes onto real functional changes or other refactorings. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 18 12月, 2012 1 次提交
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由 Peter Crosthwaite 提交于
Add the relevant CPU nr to this debug message to make IRQ debugging more informative. Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NStefan Hajnoczi <stefanha@redhat.com>
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- 11 12月, 2012 2 次提交
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由 Daniel Sangorrin 提交于
Fix a bug on the ARM GIC model where interrupts are not set pending on the correct target CPUs when they are triggered by writes to the Interrupt Set Enable or Set Pending registers. Signed-off-by: NDaniel Sangorrin <dsl@ertl.jp> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The GIC spec states that only interrupts with higher priority than the value in the GICC_PMR priority mask register are passed through to the processor. We were incorrectly allowing through interrupts with a priority equal to the specified value: correct the comparison operation to match the spec. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NIgor Mitsyanko <i.mitsyanko@samsung.com>
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- 30 10月, 2012 1 次提交
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由 Peter Maydell 提交于
Use LOG_GUEST_ERROR to report guest accesses to bad offsets. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 10月, 2012 1 次提交
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由 Avi Kivity 提交于
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: NAvi Kivity <avi@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 12 10月, 2012 2 次提交
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由 Peter Maydell 提交于
Rename the gic_state struct to match QEMU's coding style conventions for structure names, since the impending KVM-for-ARM patches will create another subclass of it. This patch was created using: sed -i 's/gic_state/GICState/g' hw/arm_gic.c hw/arm_gic_common.c \ hw/arm_gic_internal.h hw/armv7m_nvic.c Acked-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Evgeny Voevodin 提交于
s->cpu_enabled is an array, so s->cpu_enabled ? "En" : "Dis" returns "En" always. We should use s->cpu_enabled[cpu] here. Signed-off-by: NEvgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 8月, 2012 1 次提交
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由 Peter Maydell 提交于
Add the missing .class_size definition to the arm_gic_info TypeInfo. This fixes the memory corruption and possible segfault that otherwise results when the class struct is allocated at too small a size and the class init function writes off the end of it. Reported-by: NAdam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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