hw/arm_gic: fix target CPUs affected by set enable/pending ops
Fix a bug on the ARM GIC model where interrupts are not set pending on the correct target CPUs when they are triggered by writes to the Interrupt Set Enable or Set Pending registers. Signed-off-by: NDaniel Sangorrin <dsl@ertl.jp> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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