- 28 10月, 2016 1 次提交
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由 Wei Huang 提交于
This patch adds a pmu=[on/off] option to enable/disable vPMU support in guest vCPU. It allows virt tools, such as libvirt, to determine the exsitence of vPMU and configure it. Note this option is only available for cortex-a57/cortex-53/ host CPUs, but unavailable on ARMv7 and other processors. Also even though "pmu=" option is available for TCG mode, setting it doesn't turn PMU on. Signed-off-by: NWei Huang <wei@redhat.com> Reviewed-by: NAndrew Jones <drjones@redhat.com> Message-id: 1477463301-17175-2-git-send-email-wei@redhat.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 23 3月, 2016 1 次提交
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由 Markus Armbruster 提交于
Commit 57cb38b3 included qapi/error.h into qemu/osdep.h to get the Error typedef. Since then, we've moved to include qemu/osdep.h everywhere. Its file comment explains: "To avoid getting into possible circular include dependencies, this file should not include any other QEMU headers, with the exceptions of config-host.h, compiler.h, os-posix.h and os-win32.h, all of which are doing a similar job to this file and are under similar constraints." qapi/error.h doesn't do a similar job, and it doesn't adhere to similar constraints: it includes qapi-types.h. That's in excess of 100KiB of crap most .c files don't actually need. Add the typedef to qemu/typedefs.h, and include that instead of qapi/error.h. Include qapi/error.h in .c files that need it and don't get it now. Include qapi-types.h in qom/object.h for uint16List. Update scripts/clean-includes accordingly. Update it further to match reality: replace config.h by config-target.h, add sysemu/os-posix.h, sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h comment quoted above similarly. This reduces the number of objects depending on qapi/error.h from "all of them" to less than a third. Unfortunately, the number depending on qapi-types.h shrinks only a little. More work is needed for that one. Signed-off-by: NMarkus Armbruster <armbru@redhat.com> [Fix compilation without the spice devel packages. - Paolo] Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 18 2月, 2016 1 次提交
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由 Alistair Francis 提交于
Signed-off-by: NAaron Lindsay <alindsay@codeaurora.org> Signed-off-by: NAlistair Francis <alistair.francis@xilinx.com> Tested-by: NNathan Rossi <nathan@nathanrossi.com> Message-id: da0563119a9f56fd5fbdc26e7ed19a8a8457c5b9.1455060548.git.alistair.francis@xilinx.com [PMM: Use 0 for PMCEID0 values for A15 and A57 since our PMU does not currently implement any events.] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 11 2月, 2016 1 次提交
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由 Peter Maydell 提交于
Enable EL3 support for our Cortex-A53 and Cortex-A57 CPU models. We have enough implemented now to be able to run real world code at least to some extent (I can boot ARM Trusted Firmware to the point where it pulls in OP-TEE and then falls over because it doesn't have a UEFI image it can chain to). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-8-git-send-email-peter.maydell@linaro.org
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- 27 1月, 2016 1 次提交
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由 David Hildenbrand 提交于
This patch provides the name of the architecture in the target.xml if available. This allows the remote gdb to detect the target architecture on its own - so there is no need to specify it manually (e.g. if gdb is started without a binary) using "set arch *arch_name*". The name of the architecture is provided by a callback that can be implemented by all architectures. The arm implementation has special handling for iwmmxt and returns arm otherwise. This can be extended if necessary. Signed-off-by: NDavid Hildenbrand <dahi@linux.vnet.ibm.com> Acked-by: NCornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: NChristian Borntraeger <borntraeger@de.ibm.com> [rework to use a callback] Message-Id: <1449144881-130935-1-git-send-email-borntraeger@de.ibm.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NCornelia Huck <cornelia.huck@de.ibm.com>
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- 21 1月, 2016 1 次提交
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由 Peter Maydell 提交于
If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be taken to an exception level which is running AArch32 (if only EL0 and EL1 are present then EL1 must be AArch64 and all exceptions are taken to AArch64). To support this we need to have a single implementation of the CPU do_interrupt() method which can handle both 32 and 64 bit exception entry. Pull the common parts of aarch64_cpu_do_interrupt() and arm_cpu_do_interrupt() out into a new function which calls either the AArch32 or AArch64 specific entry code once it has worked out which one is needed. We temporarily special-case the handling of EXCP_SEMIHOST to avoid an assertion in arm_el_is_aa64(); the next patch will pull all the semihosting handling out to the arm_cpu_do_interrupt() level (since semihosting semantics depend on the register width of the calling code, not on that of any higher EL). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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- 19 1月, 2016 1 次提交
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由 Peter Maydell 提交于
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NDaniel P. Berrange <berrange@redhat.com> Message-id: 1449505425-32022-3-git-send-email-peter.maydell@linaro.org
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- 16 6月, 2015 2 次提交
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由 Sergey Fedorov 提交于
According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57. Signed-off-by: NSergey Fedorov <serge.fdrv@gmail.com> Message-id: 1433321048-23793-2-git-send-email-serge.fdrv@gmail.com Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Shannon Zhao 提交于
Since commit e3531026(target-arm: cpu64: Add support for Cortex-A53) has added Cortex-A53 cpu support for target-arm, this patch just enables it for kvm-arm. Here adding XGENE_POTENZA just makes the enum continuous. Signed-off-by: NShannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: NShannon Zhao <shannon.zhao@linaro.org> Message-id: 1433207452-4512-2-git-send-email-shannon.zhao@linaro.org [PMM: Don't add the CPU types to cpus_to_try[]; this array only lists old CPUs which were supported in pre-PREFERRED_TARGET kernels] Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 5月, 2015 2 次提交
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由 Peter Crosthwaite 提交于
Add the ARM Cortex-A53 processor definition. Similar to A57, but with different L1 I cache policy, phys addr size and different cache geometries. The cache sizes is implementation configurable, but use these values (from Xilinx Zynq MPSoC) as a default until cache size configurability is added. Acked-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Crosthwaite 提交于
Rename some A57 CP register variables in preparation for support for Cortex A53. Use "a57_a53" to describe the shareable features. Some of the CP15 registers (such as ACTLR) are specific to implementation, but we currently just RAZ them so continue with that as the policy for both A57 and A53 processors under a shared definition. Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5a5f957994677d91435190b3be1cefa6f657e274.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 11 3月, 2015 1 次提交
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由 Ryota Ozaki 提交于
Signed-off-by: NRyota Ozaki <ozaki.ryota@gmail.com> Reviewed-by: NAlistair Francis <alistair.francis@xilinx.com> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1424097799-11002-1-git-send-email-ozaki.ryota@gmail.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 13 2月, 2015 1 次提交
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由 Greg Bellows 提交于
Adds registration and get/set functions for enabling/disabling the AArch64 execution state on AArch64 CPUs. By default AArch64 execution state is enabled on AArch64 CPUs, setting the property to off, will disable the execution state. The below QEMU invocation would have AArch64 execution state disabled. $ ./qemu-system-aarch64 -machine virt -cpu cortex-a57,aarch64=off Also adds stripping of features from CPU model string in acquiring the ARM CPU by name. Signed-off-by: NGreg Bellows <greg.bellows@linaro.org> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1423736974-14254-2-git-send-email-greg.bellows@linaro.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 24 10月, 2014 2 次提交
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由 Peter Maydell 提交于
For the CPU type "any" (only used with linux-user) we were reporting the L1Ip field as 0b00, which is reserved. Change this field to 0b10 instead, indicating a VIPT icache as the comment describes. Reported-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NLaurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412966807-20844-1-git-send-email-peter.maydell@linaro.org
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由 Rob Herring 提交于
User mode emulation should never get interrupts and thus should not use the system emulation exception handler function. Remove the reference, and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add system mode only functionality to it. Signed-off-by: NRob Herring <rob.herring@linaro.org> Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-3-git-send-email-peter.maydell@linaro.org
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- 26 9月, 2014 1 次提交
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由 Richard Henderson 提交于
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: NRichard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-15-git-send-email-rth@twiddle.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 29 8月, 2014 1 次提交
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由 Peter Maydell 提交于
We implement the crypto extensions but were incorrectly reporting ID register values for the Cortex-A57 which did not advertise crypto. Use the correct values as described in the TRM. With this fix Linux correctly detects presence of the crypto features and advertises them in /proc/cpuinfo. Reported-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1408718660-7295-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 20 8月, 2014 1 次提交
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由 Peter Maydell 提交于
Allow each CPU type to specify the value for the debug ID registers, by putting them in the ARMCPU struct, and use the resulting information to only expose the correct number of watchpoint and breakpoint registers for the CPU. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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- 09 6月, 2014 4 次提交
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由 Peter Maydell 提交于
VFPv4 implies the presence of the half-precision floating point extension (which is optional in VFPv3). Add this implied rule to arm_cpu_realizefn() and remove some no-longer-needed explicit setting of the bit in initfns. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-5-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
CRC and crypto are both optional v8 extensions, so FEATURE_V8 should not imply them. Instead we should set these bits in the initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-4-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so we don't need to set them explicitly in initfns which set the V8 feature bit. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1401458125-27977-3-git-send-email-peter.maydell@linaro.org
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由 Peter Maydell 提交于
cpu64.c contains a reginfo list for the impdef registers on the Cortex-A57; however we forgot to actually call define_arm_cp_regs(), so it was sitting there doing nothing. Remedy this omission. Message-id: 1401226259-23121-1-git-send-email-peter.maydell@linaro.org Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Tested-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 18 4月, 2014 8 次提交
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由 Peter Maydell 提交于
For system mode, we may have a 64 bit CPU which is currently executing in AArch32 state; if we're dumping CPU state to the logs we should therefore show the correct state for the current execution state, rather than hardwiring it based on the type of the CPU. For consistency with how we handle translation, we leave the 32 bit dump function as the default, and have it hand off control to the 64 bit dump code if we're in AArch64 mode. Reported-by: NRob Herring <rob.herring@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
The AArch64 implementation of the set_pc method needs to be updated to handle the possibility that the CPU is in AArch32 mode; otherwise there are weird crashes when doing interprocessing in system emulation mode when an interrupt occurs and we fail to resynchronize the 32-bit PC with the TB we need to execute next. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The Cortex-A57, like most of the other ARM cores, has a CBAR register which defines the base address of the per-CPU peripherals. However it has a 64-bit view as well as a 32-bit view; expand the QOM reset-cbar property from UINT32 to UINT64 so this can be specified, and implement the 32-bit and 64-bit views of a 64-bit CBAR. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement a subset of the Cortex-A57's implementation defined system registers. We provide RAZ/WI or reads-as-constant/writes-ignored implementations of the various control and syndrome reigsters. We do not implement registers which provide direct access to and manipulation of the L1 cache, since QEMU doesn't implement caches. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
The AArch64 usermode 'any' CPU type was accidentally specified with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since ARMv8 removes Thumb2EE completely. Since we never implemented Thumb2EE anyway having the feature bit set was fairly harmless for user-mode, but the correct thing is to not set it at all. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Add Cortex-A57 processor. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Rob Herring 提交于
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or AArch32 EL0 are supported. Signed-off-by: NRob Herring <rob.herring@linaro.org> [PMM: fixed minor style nits; updated to match changes in previous patches; added some of the simpler cases of illegal-exception-return support] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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由 Peter Maydell 提交于
Implement the DC ZVA instruction, which clears a block of memory. The fast path obtains a pointer to the underlying RAM via the TCG TLB data structure so we can do a direct memset(), with fallback to a simple byte-store loop in the slow path. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net> Acked-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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- 27 2月, 2014 1 次提交
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由 Peter Maydell 提交于
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR) visible to AArch64. These are mostly simple 64-bit extensions of the existing 32 bit system registers and so can share reginfo definitions. CTR needs to have a split definition, but we can clean up the temporary user-mode implementation in favour of using the CPU-specified reset value, and implement the system-mode-required semantics of restricting its EL0 accessibility if SCTLR.UCT is not set. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
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- 14 1月, 2014 1 次提交
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由 Peter Maydell 提交于
Switch the ARMCPUInfo arrays in cpu.c and cpu64.c to use a terminator entry rather than looping based on ARRAY_SIZE. The latter causes compile warnings on some versions of gcc if the configure options happen to result in an empty array. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
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- 09 1月, 2014 1 次提交
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由 Michael S. Tsirkin 提交于
commit 5ce4f357 "target-arm: A64: add set_pc cpu method" introduces an array aarch64_cpus which is zero size if this code is built without CONFIG_USER_ONLY. In particular an attempt to iterate over this array produces a warning under gcc 4.8.2: CC aarch64-softmmu/target-arm/cpu64.o /scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’: /scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned expression < 0 is always false [-Werror=type-limits] for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) { ^ cc1: all warnings being treated as errors This is the result of ARRAY_SIZE being an unsigned type, causing "i" to be promoted to unsigned int as well. As zero size arrays are a gcc extension, it seems cleanest to add a dummy element with NULL name, and test for it during registration. We'll be able to drop this when we add more CPUs. Cc: Alexander Graf <agraf@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NStefan Weil <sw@weilnetz.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20131223145216.GA22663@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 08 1月, 2014 1 次提交
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由 Michael S. Tsirkin 提交于
commit 5ce4f357 "target-arm: A64: add set_pc cpu method" introduces an array aarch64_cpus which is zero size if this code is built without CONFIG_USER_ONLY. In particular an attempt to iterate over this array produces a warning under gcc 4.8.2: CC aarch64-softmmu/target-arm/cpu64.o /scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’: /scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned expression < 0 is always false [-Werror=type-limits] for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) { ^ cc1: all warnings being treated as errors This is the result of ARRAY_SIZE being an unsigned type, causing "i" to be promoted to unsigned int as well. As zero size arrays are a gcc extension, it seems cleanest to add a dummy element with NULL name, and test for it during registration. We'll be able to drop this when we add more CPUs. Cc: Alexander Graf <agraf@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NStefan Weil <sw@weilnetz.de> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 20131223145216.GA22663@redhat.com Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 24 12月, 2013 1 次提交
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由 Michael S. Tsirkin 提交于
commit 5ce4f357 "target-arm: A64: add set_pc cpu method" introduces an array aarch64_cpus which is zero size if this code is built without CONFIG_USER_ONLY. In particular an attempt to iterate over this array produces a warning under gcc 4.8.2: CC aarch64-softmmu/target-arm/cpu64.o /scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’: /scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned expression < 0 is always false [-Werror=type-limits] for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) { ^ cc1: all warnings being treated as errors This is the result of ARRAY_SIZE being an unsigned type, causing "i" to be promoted to unsigned int as well. As zero size arrays are a gcc extension, it seems cleanest to add a dummy element with NULL name, and test for it during registration. We'll be able to drop this when we add more CPUs. Cc: Alexander Graf <agraf@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: NMichael S. Tsirkin <mst@redhat.com> Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NStefan Weil <sw@weilnetz.de>
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- 18 12月, 2013 1 次提交
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由 Alexander Graf 提交于
When executing translation blocks we need to be able to recover our program counter. Add a method to set it for AArch64 CPUs. This covers user-mode, but for system mode emulation we will need to check if the CPU is in an AArch32 execution state. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <rth@twiddle.net>
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- 11 9月, 2013 3 次提交
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由 Alexander Graf 提交于
We want to be able to debug AArch64 guests. So let's add the respective gdb stub functions and xml descriptions that allow us to do so. Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-12-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org [PMM: dropped unused fp regs XML for now; moved 64 bit only functions to new gdbstub64.c; these are hooked up in AArch64CPU, not via ifdefs in ARMCPU] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alexander Graf 提交于
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode, registers look vastly different, instruction encoding is completely different, basically the system turns into a different machine. So let's do a simple if() in translate.c to decide whether we can handle the current code in the legacy AArch32 code or in the new AArch64 code. So far, the translation always complains about unallocated instructions. There is no emulator functionality in this patch! Signed-off-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org [PMM: * provide no-op versions of a64 functions ifndef TARGET_AARCH64; this lets us avoid #ifdefs in translate.c * insert the missing call to disas_a64_insn() * stash the insn in the DisasContext rather than reloading it in real_unallocated_encoding() ] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Create a new AArch64CPU class; all 64-bit capable ARM CPUs are subclasses of this. (Currently we only support one, the "any" CPU used by linux-user.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Message-id: 1378235544-22290-8-git-send-email-peter.maydell@linaro.org
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