Skip to content

Q
qemu

openeuler / qemu

通知 10
Star 0
Fork 0
Q
qemu
切换分支/标签
  1. 30 9月, 2014 3 次提交
    • E
      target-arm: A64: Emulate the HVC insn · 35979d71
      由 Edgar E. Iglesias 提交于 
      Signed-off-by: NEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-8-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
      35979d71
    • P
      target-arm: Don't handle c15_cpar changes via tb_flush() · c0f4af17
      由 Peter Maydell 提交于 
      At the moment we try to handle c15_cpar with the strategy of:
 * emit generated code which makes assumptions about its value
 * when the register value changes call tb_flush() to throw
   away the now-invalid generated code
This works because XScale CPUs are always uniprocessor, but
it's confusing because it suggests that the same approach can
be taken for other registers. It also means we do a tb_flush()
on CPU reset, which makes multithreaded linux-user binaries
even more likely to fail than would otherwise be the case.

Replace it with a combination of TB flags for the access
checks done on cp0/cp1 for the XScale and iwMMXt instructions,
plus a runtime check for cp2..cp13 coprocessor accesses.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1411056959-23070-1-git-send-email-peter.maydell@linaro.org
      c0f4af17
    • P
      target-arm: Implement handling of breakpoint firing · 0eacea70
      由 Peter Maydell 提交于 
      Implement handling of breakpoint event firing to correctly
inject the debug exception into the guest.

Since the breakpoint and watchpoint control register format is
very similar we adjust wp_matches() to also handle breakpoints
as well rather than using a separate function.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Message-id: 1410523465-13400-3-git-send-email-peter.maydell@linaro.org
      0eacea70
  3. 12 9月, 2014 1 次提交
  5. 20 8月, 2014 3 次提交
  7. 04 8月, 2014 2 次提交
  9. 05 6月, 2014 2 次提交
  11. 29 5月, 2014 1 次提交
  13. 28 5月, 2014 4 次提交
  15. 01 5月, 2014 1 次提交
  17. 18 4月, 2014 5 次提交
  19. 14 3月, 2014 5 次提交
  21. 10 3月, 2014 1 次提交
  23. 27 2月, 2014 1 次提交
  25. 20 2月, 2014 2 次提交
    • P
      target-arm: Drop success/fail return from cpreg read and write functions · c4241c7d
      由 Peter Maydell 提交于 
      All cpreg read and write functions now return 0, so we can clean up
their prototypes:
 * write functions return void
 * read functions return the value rather than taking a pointer
   to write the value to

This is a fairly mechanical change which makes only the bare
minimum set of changes to the callers of read and write functions.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      c4241c7d
    • P
      target-arm: Split cpreg access checks out from read/write functions · f59df3f2
      由 Peter Maydell 提交于 
      Several of the system registers handled via the ARMCPRegInfo
mechanism have access trap control bits controlling whether the
registers are accessible to lower privilege levels. Replace
the existing mechanism (allowing the read and write functions
to return EXCP_UDEF if access is denied) with a dedicated
"check access rights" function pointer in the ARMCPRegInfo.
This will allow us to simplify some of the register definitions,
which no longer need read/write functions purely to handle
the access checks.

We take the opportunity to define the return value from the
access checking function in a way that allows us to set the
correct exception syndrome information for exceptions taken
to AArch64 (which may need to distinguish access failures due
to a configurable trap or enable from other kinds of access
failure).

This commit defines the new mechanism but does not move any
of the registers across to use it.
Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
      f59df3f2
  27. 12 3月, 2013 1 次提交
  29. 24 2月, 2013 2 次提交
  31. 19 12月, 2012 1 次提交
  33. 16 12月, 2012 1 次提交
  35. 24 10月, 2012 1 次提交
  37. 05 10月, 2012 2 次提交
  39. 16 9月, 2012 1 次提交