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    target-arm: Implement SP_EL0, SP_EL1 · f502cfc2
    Peter Maydell 提交于
    Implement handling for the AArch64 SP_EL0 system register.
    This holds the EL0 stack pointer, and is only accessible when
    it's not being used as the stack pointer, ie when we're in EL1
    and EL1 is using its own stack pointer. We also provide a
    definition of the SP_EL1 register; this isn't guest visible
    as a system register for an implementation like QEMU which
    doesn't provide EL2 or EL3; however it is useful for ensuring
    the underlying state is migrated.
    
    We need to update the state fields in the CPU state whenever
    we switch stack pointers; this happens when we take an exception
    and also when SPSEL is used to change the bit in PSTATE which
    indicates which stack pointer EL1 should use.
    Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
    Reviewed-by: NPeter Crosthwaite <peter.crosthwaite@xilinx.com>
    f502cfc2
op_helper.c 10.9 KB