- 20 6月, 2012 21 次提交
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由 Peter Maydell 提交于
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme. Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is a change from previous behaviour, but a return to the behaviour of commit c3d2689d when OMAP1 support was first added -- subsequent commits have clearly accidentally relegated the OMAPCP RAZ condition to only a subset of the crn=9 space when adding support for other cores. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=7 registers to the new scheme. Note that to do this we have to distinguish some registers used on the ARM9 and ARM10 from some which are ARM1176 only. This is because the old code returned a value of 0 but always set the Z flag (by clearing env->ZF, since we store the Z flag in CPUState inverted). This is inconsistent with actual ARM CPU behaviour, which only sets flags for reads to r15 and sets them based on the top bits of the result. However it happened to work for the two common use cases for cp15 crn=7 reads: * On ARM9 and ARM10 the cache clean-and-test operations are typically done with a destination of r15 so that you can do a "loop: mrc ... ; bne loop" to keep cleaning until the cache is finally clean; always setting the Z flag means this loop terminates immediately * on ARM1176 the Cache Dirty Status Register reads as zero if the cache is dirty; returning 0 means this is correctly implemented for QEMU Since the new coprocessor register framework does the right thing of always setting flags based on the returned result for reads to r15, we need to split these up so that we can return (1<<30) for the ARM9/ARM10 registers but 0 for the ARM1176 one. This allows us to remove the nasty hack which always sets Z. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert cp15 MMU TLB control (crn=8) to new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=15 (implementation specific) registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
We RAZ/WI the entire block of crn=10 registers. Note that this actually covers not just the implementation-defined TLB lockdown registers but also a number of v7 VMSA memory attribute registers which we would need to implement to support TEX remap. We retain the previous QEMU behaviour in this conversion, though. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the MMU fault status and MPU access permission cp15 registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the (dummy) generic timer cp15 implementation. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the v7 performance monitor cp15 registers to the new scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert TLS registers to the new cp15 framework Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the various WFI and barrier instruction special cases to use cp_reginfo infrastructure. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to use arm_cp_reginfo. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Initial infrastructure for data-driven registration of coprocessor register implementations. We still fall back to the old-style switch statements pending complete conversion of all existing registers. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Make the 11MPCore report a valid value in its cache type register (the previous value appears to have been incorrectly copied from the 1136/1176). In particular, do not report that we have an aliasing VIPT cache, because this causes Linux to attempt to use the v6 block cache ops which the 11MPCore doesn't actually have. (This causes no problems currently because we over-broadly provide those ops on all cores, but prevents us correctly narrowing the block ops down to those cores which actually implement them.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 07 6月, 2012 3 次提交
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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由 Paolo Bonzini 提交于
Also drop duplicate occurrence of device-hotplug.o. Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
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- 05 6月, 2012 2 次提交
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由 Andreas Färber 提交于
In commit 1bba0dc9 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: NBlue Swirl <blauwirbel@gmail.com>
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由 Andreas Färber 提交于
Commit 3c30dd5a (target-arm: Move reset handling to arm_cpu_reset) QOM'ified CPU reset. Complete it by replacing cpu_state_reset() with cpu_reset(). Signed-off-by: NAndreas Färber <afaerber@suse.de> Acked-by: NPeter Maydell <peter.maydell@linaro.org>
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- 10 5月, 2012 2 次提交
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由 Peter Maydell 提交于
The macro definition of cpu_init meant that if cpu_arm_init() returned NULL this wouldn't result in cpu_init() itself returning NULL. This had the effect that "-cpu foo" for some unknown CPU name 'foo' would cause ARM targets to segfault rather than generating a useful error message. Fix this by making cpu_init a simple inline function. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Matt Craighead 提交于
This patch fixes a bug affecting a variety of Neon instructions, such as VQADD. Signed-off-by: NMatt Craighead <mjcraighead@gmail.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 27 4月, 2012 3 次提交
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由 Peter Maydell 提交于
Make the SETEND instruction respect the setting of bswap_code, so that in BE8 mode we UNDEF for attempts to switch into little-endian mode and nop for attempts to stay in big-endian mode. (This is the inverse of the existing handling of SETEND in the more common little-endian setup, which we use since we don't implement the architecturally-mandated dynamic endianness switching.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Move the A9 config_base_address cp15 register reset value to ARMCPU. This should become a QOM property so that the Highbank board can set it without having to pull in cpu-qom.h, but at least this avoids the implicit dependency on reset ordering that the previous workaround had. Cc: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NAndreas Färber <afaerber@suse.de>
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由 Andreas Färber 提交于
Make cpu_arm_init() return a QOM ARMCPU, so that we don't need to obtain an ARMCPU through arm_env_get_cpu() in machine init code. This requires to adjust the inclusion site of cpu-qom.h and in turn, forward-looking, to homogenize its include order. cpu_init() must still return a CPUARMState for backwards and cross-target compatibility, so adjust the cpu_init macro. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 22 4月, 2012 9 次提交
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由 Peter Maydell 提交于
Now that cpu_reset_model_id() has gone we can move the reset code over to the class reset function and have cpu_state_reset simply do a reset on the CPU QOM object. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
cpu_reset_model_id() is now empty and we can remove it. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move cache ID register reset out of cpu_reset_model_id() by creating a field for the reset value in ARMCPU and setting it up in the cpu specific init functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset; since these registers are only accessible on CPUs with the OMAPCP feature set there's no need to guard this reset with either a CPUID or feature bit check. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move feature register value setup to per-CPU init functions. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move the iWMMXT wCID reset to cpu_state_reset(). Since we use the same value for all CPUs with this feature (with the major/minor revision fields set to the QEMU specific 'Q' value) there's no need to create an ARMCPU field just for this. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
None of the machines in QEMU offer a JTAG debug interface, so this info was unused. Further, the PXA250 ID contradicts the February 2002 Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Move the reset value of SCTLR to ARMCPU, initialised in the per-cpu init functions. It can then be reset by a simple copy, and we can drop the code from cpu_reset_model_id(). Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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由 Peter Maydell 提交于
Move CTR (cache type register) value to an ARMCPU field set up by per-cpu init fns. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Acked-by: NAndreas Färber <afaerber@suse.de>
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