- 12 2月, 2019 2 次提交
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由 Michael Clark 提交于
* Add riscv prefix to raise_exception function * Add riscv prefix to CSR read/write functions * Add riscv prefix to signal handler function * Add riscv prefix to get fflags function * Remove redundant declaration of riscv_cpu_init and rename cpu_riscv_init to riscv_cpu_init * rename riscv_set_mode to riscv_cpu_set_mode Signed-off-by: NMichael Clark <mjc@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Michael Clark 提交于
This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: NMichael Clark <mjc@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Co-authored-by: NMatthew Suozzo <msuozzo@google.com> Co-authored-by: NMichael Clark <mjc@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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- 09 1月, 2019 1 次提交
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由 Michael Clark 提交于
Previous CSR code uses csr_read_helper and csr_write_helper to update CSR registers however this interface prevents atomic read/modify/write CSR operations; in addition there is no trap-free method to access to CSRs due to the monolithic CSR functions call longjmp. The current iCSR interface is not safe to be called by target/riscv/gdbstub.c as privilege checks or missing CSRs may call longjmp to generate exceptions. It needs to indicate existence so traps can be generated in the CSR instruction helpers. This commit moves CSR access from the monolithic switch statements in target/riscv/op_helper.c into modular read/write functions in target/riscv/csr.c using a new function pointer table for dispatch (which can later be used to allow CPUs to hook up model specific CSRs). A read/modify/write interface is added to support atomic CSR operations and a non-trapping interface is added to allow exception-free access to CSRs by the debugger. The CSR functions and CSR dispatch table are ordered to match The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.10, 2.2 CSR Listing. An API is added to allow derived cpu instances to modify or implement new CSR operations. Signed-off-by: NMichael Clark <mjc@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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- 18 10月, 2018 3 次提交
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由 Michael Clark 提交于
* Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Michael Clark 提交于
This patch makes op_helper.c contain only instruction operation helpers used by translate.c and moves any unrelated cpu helpers into cpu_helper.c. No logic is changed by this patch. Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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由 Michael Clark 提交于
Change the API of riscv_set_local_interrupt to take a write mask and value to allow setting and clearing of multiple local interrupts atomically in a single call. Rename the new function to riscv_cpu_update_mip. Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com> Reviewed-by: NPalmer Dabbelt <palmer@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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- 08 6月, 2018 1 次提交
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由 Philippe Mathieu-Daudé 提交于
Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180606152128.449-11-f4bug@amsat.org Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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- 06 5月, 2018 6 次提交
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由 Michael Clark 提交于
These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: NMichael Clark <mjc@sifive.com>
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由 Michael Clark 提交于
Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: NMichael Clark <mjc@sifive.com>
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由 Michael Clark 提交于
Previously the mycycle/minstret CSRs and rdcycle/rdinstret psuedo instructions would return the time as a proxy for an increasing instruction counter in the absence of having a precise instruction count. If QEMU is invoked with -icount, the mcycle/minstret CSRs and rdcycle/rdinstret psuedo instructions will return the instruction count. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
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由 Michael Clark 提交于
Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >= v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <= v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >= v1.10 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: NMichael Clark <mjc@sifive.com>
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由 Michael Clark 提交于
The mstatus.MXR alias in sstatus should only be writable by S-mode if the privileged ISA version >= v1.10. Also MXR was masked in sstatus CSR read but not sstatus CSR writes. Now we correctly mask sstatus.mxr in both read and write. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
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由 Michael Clark 提交于
satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NAlistair Francis <alistair.francis@wdc.com>
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- 30 3月, 2018 1 次提交
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由 Michael Clark 提交于
This change is a workaround for a bug where mstatus.FS is not correctly reporting dirty after operations that modify floating point registers. This a critical bug or RISC-V in QEMU as it results in floating point register file corruption when running SMP Linux due to task migration and possibly uniprocessor Linux if more than one process is using the FPU. This workaround will return dirty if mstatus.FS is switched from off to initial or clean. According to the specification it is legal for an implementation to return only off, or dirty. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NRichard W.M. Jones <rjones@redhat.com> Signed-off-by: NMichael Clark <mjc@sifive.com> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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- 07 3月, 2018 1 次提交
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由 Michael Clark 提交于
Privileged control and status register helpers and page fault handling. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Signed-off-by: NSagar Karandikar <sagark@eecs.berkeley.edu> Signed-off-by: NMichael Clark <mjc@sifive.com>
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