RISC-V: Implement mstatus.TSR/TW/TVM
This adds the necessary minimum to support S-mode virtualization for priv ISA >= v1.10 Signed-off-by: NMichael Clark <mjc@sifive.com> Signed-off-by: NAlistair Francis <alistair.francis@wdc.com> Co-authored-by: NMatthew Suozzo <msuozzo@google.com> Co-authored-by: NMichael Clark <mjc@sifive.com> Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
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