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  1. 13 12月, 2008 1 次提交
  3. 08 12月, 2008 4 次提交
  5. 02 12月, 2008 1 次提交
  7. 22 11月, 2008 2 次提交
    • A
      SH4: Switch serial emulation to qemu_irq · 4e7ed2d1
      由 aurel32 提交于 
      This patches makes SH serial emulation use qemu_irq in its interface.

        * hw/sh.h (sh_serial_init): Take qemu_irq, not intc_source.
        * hw/sh7750.c (sh7750_init): Adjust.
        * hw/sh_intc.c (sh_intc_set_irq): Don't assert or deassert
        irq more than once.
        * hw/sh_serial.c (sh_serial_state): Use qemu_irq, not intc_source.
        (sh_serial_clear_fifo, sh_serial_ioport_write)
        (sh_serial_receive_byte): Adjust.
        (sh_serial_init): Take qemu_irq, not intc_source.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5769 c046a42c-6fe2-441c-8c8c-71466251a162
      4e7ed2d1
    • A
      SH4: Use qemu_irq in timer emulation. · 96e2fc41
      由 aurel32 提交于 
              * hw/sh.h (tmu012_init): Accept qemu_irq, not intc_source.
        * hw/sh7750.c (sh7750_init): Pass qemu_irq to tmu012_init.
        * hw/sh_intc.c (sh_intc_set_irq): New.
        (sh_intc_init): Allocate irqs.
        * hw/sh_intc.h (struct intc_desc): New field irqs.
        * hw/sh_timer.c (sh_timer_state): Use qemu_irq, not intc_source.
        (sh_timer_update): Use qemu_set_irq, not sh_intc_toggle_source.
        (sh_timer_init, tmu012_init): Adjust.

(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5768 c046a42c-6fe2-441c-8c8c-71466251a162
      96e2fc41
  9. 03 9月, 2008 1 次提交
    • A
      sh4: CPU versioning. · 0fd3ca30
      由 aurel32 提交于 
      Trivial patch adding CPU listing and the ability to do per-subtype
CVR/PVR/PRR values. Presently SH7750R and SH7751R definitions are
provided, as these are the ones in present use in-tree.

The CVR value for SH7751R is intentionally restricted so the kernel
boots, though this will want to be switched to the proper CVR value
once system emulation has sufficiently stabilized.

This also makes it trivial to abstract subtype specific registers like
MMU_PTEA and to set up feature bits in line with the kernel probing for
things like conditionalizing FPU/DSP context.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Signed-off-by: NAurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5133 c046a42c-6fe2-441c-8c8c-71466251a162
      0fd3ca30
  11. 22 8月, 2008 2 次提交
    • A
      [sh4] MMU bug fix · 06afe2c8
      由 aurel32 提交于 
      Some bugs on SH4 MMU are fixed.

- When a TLB entry is overwritten or invalidated, tlb_flush_page() should be
  invoked to invalidate old entry.
- When a ASID is changed, tlb_flush() should be invoke to invalidate entries
  which have old ASID.
- The check for shared bit in TLB entry causes multiple TLB hit exception.
  As SH3's MMU, shared bit is ignored.
- ASID is used when MMUCR's SV bit or SR's MD bit is zero.
  No need to check both bits are zero.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5068 c046a42c-6fe2-441c-8c8c-71466251a162
      06afe2c8
    • A
      [sh4] memory mapped TLB entries · 29e179bc
      由 aurel32 提交于 
      SH4 MMU's memory mapped TLB feature is implemented.
SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry,
but does not to read it. So only memory write feature is implemented.
Work on memory read feature is left.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5067 c046a42c-6fe2-441c-8c8c-71466251a162
      29e179bc
  13. 16 7月, 2008 1 次提交
  15. 10 5月, 2008 2 次提交
  17. 12 12月, 2007 1 次提交
  19. 02 12月, 2007 1 次提交
  21. 18 11月, 2007 1 次提交
  23. 12 11月, 2007 1 次提交
  25. 05 10月, 2007 1 次提交
  27. 30 9月, 2007 4 次提交
  29. 17 9月, 2007 1 次提交
  31. 28 1月, 2007 1 次提交
  33. 26 6月, 2006 1 次提交
  35. 28 4月, 2006 1 次提交