cpu.h 60.8 KB
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/*
 * i386 virtual CPU header
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 *
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 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#ifndef I386_CPU_H
#define I386_CPU_H
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#include "qemu-common.h"
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#include "cpu-qom.h"
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#include "hyperv-proto.h"
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#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
#else
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#define TARGET_LONG_BITS 32
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#endif
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#include "exec/cpu-defs.h"

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/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)

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/* Maximum instruction code size */
#define TARGET_MAX_INSN_SIZE 16

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/* support for self modifying code even if the modified instruction is
   close to the modifying instruction */
#define TARGET_HAS_PRECISE_SMC

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#ifdef TARGET_X86_64
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#define I386_ELF_MACHINE  EM_X86_64
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#define ELF_MACHINE_UNAME "x86_64"
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#else
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#define I386_ELF_MACHINE  EM_386
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#define ELF_MACHINE_UNAME "i686"
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#endif

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#define CPUArchState struct CPUX86State
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enum {
    R_EAX = 0,
    R_ECX = 1,
    R_EDX = 2,
    R_EBX = 3,
    R_ESP = 4,
    R_EBP = 5,
    R_ESI = 6,
    R_EDI = 7,
    R_R8 = 8,
    R_R9 = 9,
    R_R10 = 10,
    R_R11 = 11,
    R_R12 = 12,
    R_R13 = 13,
    R_R14 = 14,
    R_R15 = 15,
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    R_AL = 0,
    R_CL = 1,
    R_DL = 2,
    R_BL = 3,
    R_AH = 4,
    R_CH = 5,
    R_DH = 6,
    R_BH = 7,
};
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typedef enum X86Seg {
    R_ES = 0,
    R_CS = 1,
    R_SS = 2,
    R_DS = 3,
    R_FS = 4,
    R_GS = 5,
    R_LDTR = 6,
    R_TR = 7,
} X86Seg;
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/* segment descriptor fields */
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#define DESC_G_SHIFT    23
#define DESC_G_MASK     (1 << DESC_G_SHIFT)
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#define DESC_B_SHIFT    22
#define DESC_B_MASK     (1 << DESC_B_SHIFT)
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#define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
#define DESC_L_MASK     (1 << DESC_L_SHIFT)
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#define DESC_AVL_SHIFT  20
#define DESC_AVL_MASK   (1 << DESC_AVL_SHIFT)
#define DESC_P_SHIFT    15
#define DESC_P_MASK     (1 << DESC_P_SHIFT)
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#define DESC_DPL_SHIFT  13
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#define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
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#define DESC_S_SHIFT    12
#define DESC_S_MASK     (1 << DESC_S_SHIFT)
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#define DESC_TYPE_SHIFT 8
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#define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
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#define DESC_A_MASK     (1 << 8)

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#define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
#define DESC_C_MASK     (1 << 10) /* code: conforming */
#define DESC_R_MASK     (1 << 9)  /* code: readable */
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#define DESC_E_MASK     (1 << 10) /* data: expansion direction */
#define DESC_W_MASK     (1 << 9)  /* data: writable */

#define DESC_TSS_BUSY_MASK (1 << 9)
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/* eflags masks */
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#define CC_C    0x0001
#define CC_P    0x0004
#define CC_A    0x0010
#define CC_Z    0x0040
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#define CC_S    0x0080
#define CC_O    0x0800

#define TF_SHIFT   8
#define IOPL_SHIFT 12
#define VM_SHIFT   17

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#define TF_MASK                 0x00000100
#define IF_MASK                 0x00000200
#define DF_MASK                 0x00000400
#define IOPL_MASK               0x00003000
#define NT_MASK                 0x00004000
#define RF_MASK                 0x00010000
#define VM_MASK                 0x00020000
#define AC_MASK                 0x00040000
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#define VIF_MASK                0x00080000
#define VIP_MASK                0x00100000
#define ID_MASK                 0x00200000

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/* hidden flags - used internally by qemu to represent additional cpu
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   states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
   avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
   positions to ease oring with eflags. */
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/* current cpl */
#define HF_CPL_SHIFT         0
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
#define HF_CS32_SHIFT        4
#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
#define HF_PE_SHIFT          7
#define HF_TF_SHIFT          8 /* must be same as eflags */
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#define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
#define HF_EM_SHIFT         10
#define HF_TS_SHIFT         11
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#define HF_IOPL_SHIFT       12 /* must be same as eflags */
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#define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
#define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
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#define HF_RF_SHIFT         16 /* must be same as eflags */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_AC_SHIFT         18 /* must be same as eflags */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
#define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
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#define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
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#define HF_SMAP_SHIFT       23 /* CR4.SMAP */
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#define HF_IOBPT_SHIFT      24 /* an io breakpoint enabled */
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#define HF_MPX_EN_SHIFT     25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
#define HF_MPX_IU_SHIFT     26 /* BND registers in-use */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
#define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
#define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
#define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
#define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
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#define HF_PE_MASK           (1 << HF_PE_SHIFT)
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#define HF_TF_MASK           (1 << HF_TF_SHIFT)
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#define HF_MP_MASK           (1 << HF_MP_SHIFT)
#define HF_EM_MASK           (1 << HF_EM_SHIFT)
#define HF_TS_MASK           (1 << HF_TS_SHIFT)
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#define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
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#define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_RF_MASK           (1 << HF_RF_SHIFT)
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#define HF_VM_MASK           (1 << HF_VM_SHIFT)
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#define HF_AC_MASK           (1 << HF_AC_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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#define HF_SMAP_MASK         (1 << HF_SMAP_SHIFT)
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#define HF_IOBPT_MASK        (1 << HF_IOBPT_SHIFT)
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#define HF_MPX_EN_MASK       (1 << HF_MPX_EN_SHIFT)
#define HF_MPX_IU_MASK       (1 << HF_MPX_IU_SHIFT)
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/* hflags2 */

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#define HF2_GIF_SHIFT            0 /* if set CPU takes interrupts */
#define HF2_HIF_SHIFT            1 /* value of IF_MASK when entering SVM */
#define HF2_NMI_SHIFT            2 /* CPU serving NMI */
#define HF2_VINTR_SHIFT          3 /* value of V_INTR_MASKING bit */
#define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
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#define HF2_MPX_PR_SHIFT         5 /* BNDCFGx.BNDPRESERVE */
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#define HF2_NPT_SHIFT            6 /* Nested Paging enabled */
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#define HF2_GIF_MASK            (1 << HF2_GIF_SHIFT)
#define HF2_HIF_MASK            (1 << HF2_HIF_SHIFT)
#define HF2_NMI_MASK            (1 << HF2_NMI_SHIFT)
#define HF2_VINTR_MASK          (1 << HF2_VINTR_SHIFT)
#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
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#define HF2_MPX_PR_MASK         (1 << HF2_MPX_PR_SHIFT)
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#define HF2_NPT_MASK            (1 << HF2_NPT_SHIFT)
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#define CR0_PE_SHIFT 0
#define CR0_MP_SHIFT 1

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#define CR0_PE_MASK  (1U << 0)
#define CR0_MP_MASK  (1U << 1)
#define CR0_EM_MASK  (1U << 2)
#define CR0_TS_MASK  (1U << 3)
#define CR0_ET_MASK  (1U << 4)
#define CR0_NE_MASK  (1U << 5)
#define CR0_WP_MASK  (1U << 16)
#define CR0_AM_MASK  (1U << 18)
#define CR0_PG_MASK  (1U << 31)

#define CR4_VME_MASK  (1U << 0)
#define CR4_PVI_MASK  (1U << 1)
#define CR4_TSD_MASK  (1U << 2)
#define CR4_DE_MASK   (1U << 3)
#define CR4_PSE_MASK  (1U << 4)
#define CR4_PAE_MASK  (1U << 5)
#define CR4_MCE_MASK  (1U << 6)
#define CR4_PGE_MASK  (1U << 7)
#define CR4_PCE_MASK  (1U << 8)
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#define CR4_OSFXSR_SHIFT 9
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#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
#define CR4_OSXMMEXCPT_MASK  (1U << 10)
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#define CR4_LA57_MASK   (1U << 12)
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#define CR4_VMXE_MASK   (1U << 13)
#define CR4_SMXE_MASK   (1U << 14)
#define CR4_FSGSBASE_MASK (1U << 16)
#define CR4_PCIDE_MASK  (1U << 17)
#define CR4_OSXSAVE_MASK (1U << 18)
#define CR4_SMEP_MASK   (1U << 20)
#define CR4_SMAP_MASK   (1U << 21)
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#define CR4_PKE_MASK   (1U << 22)
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#define DR6_BD          (1 << 13)
#define DR6_BS          (1 << 14)
#define DR6_BT          (1 << 15)
#define DR6_FIXED_1     0xffff0ff0

#define DR7_GD          (1 << 13)
#define DR7_TYPE_SHIFT  16
#define DR7_LEN_SHIFT   18
#define DR7_FIXED_1     0x00000400
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#define DR7_GLOBAL_BP_MASK   0xaa
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#define DR7_LOCAL_BP_MASK    0x55
#define DR7_MAX_BP           4
#define DR7_TYPE_BP_INST     0x0
#define DR7_TYPE_DATA_WR     0x1
#define DR7_TYPE_IO_RW       0x2
#define DR7_TYPE_DATA_RW     0x3
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#define PG_PRESENT_BIT  0
#define PG_RW_BIT       1
#define PG_USER_BIT     2
#define PG_PWT_BIT      3
#define PG_PCD_BIT      4
#define PG_ACCESSED_BIT 5
#define PG_DIRTY_BIT    6
#define PG_PSE_BIT      7
#define PG_GLOBAL_BIT   8
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#define PG_PSE_PAT_BIT  12
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#define PG_PKRU_BIT     59
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#define PG_NX_BIT       63
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#define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
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#define PG_RW_MASK       (1 << PG_RW_BIT)
#define PG_USER_MASK     (1 << PG_USER_BIT)
#define PG_PWT_MASK      (1 << PG_PWT_BIT)
#define PG_PCD_MASK      (1 << PG_PCD_BIT)
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#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
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#define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
#define PG_PSE_MASK      (1 << PG_PSE_BIT)
#define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
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#define PG_PSE_PAT_MASK  (1 << PG_PSE_PAT_BIT)
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#define PG_ADDRESS_MASK  0x000ffffffffff000LL
#define PG_HI_RSVD_MASK  (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
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#define PG_HI_USER_MASK  0x7ff0000000000000LL
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#define PG_PKRU_MASK     (15ULL << PG_PKRU_BIT)
#define PG_NX_MASK       (1ULL << PG_NX_BIT)
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#define PG_ERROR_W_BIT     1

#define PG_ERROR_P_MASK    0x01
#define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
#define PG_ERROR_U_MASK    0x04
#define PG_ERROR_RSVD_MASK 0x08
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#define PG_ERROR_I_D_MASK  0x10
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#define PG_ERROR_PK_MASK   0x20
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#define MCG_CTL_P       (1ULL<<8)   /* MCG_CAP register available */
#define MCG_SER_P       (1ULL<<24) /* MCA recovery/new status bits */
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#define MCG_LMCE_P      (1ULL<<27) /* Local Machine Check Supported */
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#define MCE_CAP_DEF     (MCG_CTL_P|MCG_SER_P)
#define MCE_BANKS_DEF   10
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#define MCG_CAP_BANKS_MASK 0xff

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#define MCG_STATUS_RIPV (1ULL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV (1ULL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP (1ULL<<2)   /* machine check in progress */
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#define MCG_STATUS_LMCE (1ULL<<3)   /* Local MCE signaled */

#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
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#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
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/* MISC register defines */
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#define MCM_ADDR_SEGOFF  0      /* segment offset */
#define MCM_ADDR_LINEAR  1      /* linear address */
#define MCM_ADDR_PHYS    2      /* physical address */
#define MCM_ADDR_MEM     3      /* memory address */
#define MCM_ADDR_GENERIC 7      /* generic */
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#define MSR_IA32_TSC                    0x10
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#define MSR_IA32_APICBASE               0x1b
#define MSR_IA32_APICBASE_BSP           (1<<8)
#define MSR_IA32_APICBASE_ENABLE        (1<<11)
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#define MSR_IA32_APICBASE_EXTD          (1 << 10)
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#define MSR_IA32_APICBASE_BASE          (0xfffffU<<12)
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#define MSR_IA32_FEATURE_CONTROL        0x0000003a
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#define MSR_TSC_ADJUST                  0x0000003b
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#define MSR_IA32_SPEC_CTRL              0x48
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#define MSR_VIRT_SSBD                   0xc001011f
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#define MSR_IA32_TSCDEADLINE            0x6e0
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#define FEATURE_CONTROL_LOCKED                    (1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
#define FEATURE_CONTROL_LMCE                      (1<<20)

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#define MSR_P6_PERFCTR0                 0xc1

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#define MSR_IA32_SMBASE                 0x9e
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#define MSR_SMI_COUNT                   0x34
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#define MSR_MTRRcap                     0xfe
#define MSR_MTRRcap_VCNT                8
#define MSR_MTRRcap_FIXRANGE_SUPPORT    (1 << 8)
#define MSR_MTRRcap_WC_SUPPORTED        (1 << 10)
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#define MSR_IA32_SYSENTER_CS            0x174
#define MSR_IA32_SYSENTER_ESP           0x175
#define MSR_IA32_SYSENTER_EIP           0x176

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#define MSR_MCG_CAP                     0x179
#define MSR_MCG_STATUS                  0x17a
#define MSR_MCG_CTL                     0x17b
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#define MSR_MCG_EXT_CTL                 0x4d0
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#define MSR_P6_EVNTSEL0                 0x186

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#define MSR_IA32_PERF_STATUS            0x198

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#define MSR_IA32_MISC_ENABLE            0x1a0
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/* Indicates good rep/movs microcode on some processors: */
#define MSR_IA32_MISC_ENABLE_DEFAULT    1

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#define MSR_MTRRphysBase(reg)           (0x200 + 2 * (reg))
#define MSR_MTRRphysMask(reg)           (0x200 + 2 * (reg) + 1)

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#define MSR_MTRRphysIndex(addr)         ((((addr) & ~1u) - 0x200) / 2)

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#define MSR_MTRRfix64K_00000            0x250
#define MSR_MTRRfix16K_80000            0x258
#define MSR_MTRRfix16K_A0000            0x259
#define MSR_MTRRfix4K_C0000             0x268
#define MSR_MTRRfix4K_C8000             0x269
#define MSR_MTRRfix4K_D0000             0x26a
#define MSR_MTRRfix4K_D8000             0x26b
#define MSR_MTRRfix4K_E0000             0x26c
#define MSR_MTRRfix4K_E8000             0x26d
#define MSR_MTRRfix4K_F0000             0x26e
#define MSR_MTRRfix4K_F8000             0x26f
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#define MSR_PAT                         0x277

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#define MSR_MTRRdefType                 0x2ff
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#define MSR_CORE_PERF_FIXED_CTR0        0x309
#define MSR_CORE_PERF_FIXED_CTR1        0x30a
#define MSR_CORE_PERF_FIXED_CTR2        0x30b
#define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
#define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
#define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
#define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
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#define MSR_MC0_CTL                     0x400
#define MSR_MC0_STATUS                  0x401
#define MSR_MC0_ADDR                    0x402
#define MSR_MC0_MISC                    0x403
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#define MSR_IA32_RTIT_OUTPUT_BASE       0x560
#define MSR_IA32_RTIT_OUTPUT_MASK       0x561
#define MSR_IA32_RTIT_CTL               0x570
#define MSR_IA32_RTIT_STATUS            0x571
#define MSR_IA32_RTIT_CR3_MATCH         0x572
#define MSR_IA32_RTIT_ADDR0_A           0x580
#define MSR_IA32_RTIT_ADDR0_B           0x581
#define MSR_IA32_RTIT_ADDR1_A           0x582
#define MSR_IA32_RTIT_ADDR1_B           0x583
#define MSR_IA32_RTIT_ADDR2_A           0x584
#define MSR_IA32_RTIT_ADDR2_B           0x585
#define MSR_IA32_RTIT_ADDR3_A           0x586
#define MSR_IA32_RTIT_ADDR3_B           0x587
#define MAX_RTIT_ADDRS                  8

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#define MSR_EFER                        0xc0000080

#define MSR_EFER_SCE   (1 << 0)
#define MSR_EFER_LME   (1 << 8)
#define MSR_EFER_LMA   (1 << 10)
#define MSR_EFER_NXE   (1 << 11)
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#define MSR_EFER_SVME  (1 << 12)
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#define MSR_EFER_FFXSR (1 << 14)

#define MSR_STAR                        0xc0000081
#define MSR_LSTAR                       0xc0000082
#define MSR_CSTAR                       0xc0000083
#define MSR_FMASK                       0xc0000084
#define MSR_FSBASE                      0xc0000100
#define MSR_GSBASE                      0xc0000101
#define MSR_KERNELGSBASE                0xc0000102
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#define MSR_TSC_AUX                     0xc0000103
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#define MSR_VM_HSAVE_PA                 0xc0010117

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#define MSR_IA32_BNDCFGS                0x00000d90
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#define MSR_IA32_XSS                    0x00000da0
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#define XSTATE_FP_BIT                   0
#define XSTATE_SSE_BIT                  1
#define XSTATE_YMM_BIT                  2
#define XSTATE_BNDREGS_BIT              3
#define XSTATE_BNDCSR_BIT               4
#define XSTATE_OPMASK_BIT               5
#define XSTATE_ZMM_Hi256_BIT            6
#define XSTATE_Hi16_ZMM_BIT             7
#define XSTATE_PKRU_BIT                 9

#define XSTATE_FP_MASK                  (1ULL << XSTATE_FP_BIT)
#define XSTATE_SSE_MASK                 (1ULL << XSTATE_SSE_BIT)
#define XSTATE_YMM_MASK                 (1ULL << XSTATE_YMM_BIT)
#define XSTATE_BNDREGS_MASK             (1ULL << XSTATE_BNDREGS_BIT)
#define XSTATE_BNDCSR_MASK              (1ULL << XSTATE_BNDCSR_BIT)
#define XSTATE_OPMASK_MASK              (1ULL << XSTATE_OPMASK_BIT)
#define XSTATE_ZMM_Hi256_MASK           (1ULL << XSTATE_ZMM_Hi256_BIT)
#define XSTATE_Hi16_ZMM_MASK            (1ULL << XSTATE_Hi16_ZMM_BIT)
#define XSTATE_PKRU_MASK                (1ULL << XSTATE_PKRU_BIT)
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/* CPUID feature words */
typedef enum FeatureWord {
    FEAT_1_EDX,         /* CPUID[1].EDX */
    FEAT_1_ECX,         /* CPUID[1].ECX */
    FEAT_7_0_EBX,       /* CPUID[EAX=7,ECX=0].EBX */
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    FEAT_7_0_ECX,       /* CPUID[EAX=7,ECX=0].ECX */
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    FEAT_7_0_EDX,       /* CPUID[EAX=7,ECX=0].EDX */
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    FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
    FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
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    FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
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    FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
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    FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
    FEAT_KVM,           /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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    FEAT_KVM_HINTS,     /* CPUID[4000_0001].EDX */
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    FEAT_HYPERV_EAX,    /* CPUID[4000_0003].EAX */
    FEAT_HYPERV_EBX,    /* CPUID[4000_0003].EBX */
    FEAT_HYPERV_EDX,    /* CPUID[4000_0003].EDX */
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    FEAT_SVM,           /* CPUID[8000_000A].EDX */
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    FEAT_XSAVE,         /* CPUID[EAX=0xd,ECX=1].EAX */
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    FEAT_6_EAX,         /* CPUID[6].EAX */
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    FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
    FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
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    FEATURE_WORDS,
} FeatureWord;

typedef uint32_t FeatureWordArray[FEATURE_WORDS];

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/* cpuid_features bits */
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#define CPUID_FP87 (1U << 0)
#define CPUID_VME  (1U << 1)
#define CPUID_DE   (1U << 2)
#define CPUID_PSE  (1U << 3)
#define CPUID_TSC  (1U << 4)
#define CPUID_MSR  (1U << 5)
#define CPUID_PAE  (1U << 6)
#define CPUID_MCE  (1U << 7)
#define CPUID_CX8  (1U << 8)
#define CPUID_APIC (1U << 9)
#define CPUID_SEP  (1U << 11) /* sysenter/sysexit */
#define CPUID_MTRR (1U << 12)
#define CPUID_PGE  (1U << 13)
#define CPUID_MCA  (1U << 14)
#define CPUID_CMOV (1U << 15)
#define CPUID_PAT  (1U << 16)
#define CPUID_PSE36   (1U << 17)
#define CPUID_PN   (1U << 18)
#define CPUID_CLFLUSH (1U << 19)
#define CPUID_DTS (1U << 21)
#define CPUID_ACPI (1U << 22)
#define CPUID_MMX  (1U << 23)
#define CPUID_FXSR (1U << 24)
#define CPUID_SSE  (1U << 25)
#define CPUID_SSE2 (1U << 26)
#define CPUID_SS (1U << 27)
#define CPUID_HT (1U << 28)
#define CPUID_TM (1U << 29)
#define CPUID_IA64 (1U << 30)
#define CPUID_PBE (1U << 31)

#define CPUID_EXT_SSE3     (1U << 0)
#define CPUID_EXT_PCLMULQDQ (1U << 1)
#define CPUID_EXT_DTES64   (1U << 2)
#define CPUID_EXT_MONITOR  (1U << 3)
#define CPUID_EXT_DSCPL    (1U << 4)
#define CPUID_EXT_VMX      (1U << 5)
#define CPUID_EXT_SMX      (1U << 6)
#define CPUID_EXT_EST      (1U << 7)
#define CPUID_EXT_TM2      (1U << 8)
#define CPUID_EXT_SSSE3    (1U << 9)
#define CPUID_EXT_CID      (1U << 10)
#define CPUID_EXT_FMA      (1U << 12)
#define CPUID_EXT_CX16     (1U << 13)
#define CPUID_EXT_XTPR     (1U << 14)
#define CPUID_EXT_PDCM     (1U << 15)
#define CPUID_EXT_PCID     (1U << 17)
#define CPUID_EXT_DCA      (1U << 18)
#define CPUID_EXT_SSE41    (1U << 19)
#define CPUID_EXT_SSE42    (1U << 20)
#define CPUID_EXT_X2APIC   (1U << 21)
#define CPUID_EXT_MOVBE    (1U << 22)
#define CPUID_EXT_POPCNT   (1U << 23)
#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
#define CPUID_EXT_AES      (1U << 25)
#define CPUID_EXT_XSAVE    (1U << 26)
#define CPUID_EXT_OSXSAVE  (1U << 27)
#define CPUID_EXT_AVX      (1U << 28)
#define CPUID_EXT_F16C     (1U << 29)
#define CPUID_EXT_RDRAND   (1U << 30)
#define CPUID_EXT_HYPERVISOR  (1U << 31)

#define CPUID_EXT2_FPU     (1U << 0)
#define CPUID_EXT2_VME     (1U << 1)
#define CPUID_EXT2_DE      (1U << 2)
#define CPUID_EXT2_PSE     (1U << 3)
#define CPUID_EXT2_TSC     (1U << 4)
#define CPUID_EXT2_MSR     (1U << 5)
#define CPUID_EXT2_PAE     (1U << 6)
#define CPUID_EXT2_MCE     (1U << 7)
#define CPUID_EXT2_CX8     (1U << 8)
#define CPUID_EXT2_APIC    (1U << 9)
#define CPUID_EXT2_SYSCALL (1U << 11)
#define CPUID_EXT2_MTRR    (1U << 12)
#define CPUID_EXT2_PGE     (1U << 13)
#define CPUID_EXT2_MCA     (1U << 14)
#define CPUID_EXT2_CMOV    (1U << 15)
#define CPUID_EXT2_PAT     (1U << 16)
#define CPUID_EXT2_PSE36   (1U << 17)
#define CPUID_EXT2_MP      (1U << 19)
#define CPUID_EXT2_NX      (1U << 20)
#define CPUID_EXT2_MMXEXT  (1U << 22)
#define CPUID_EXT2_MMX     (1U << 23)
#define CPUID_EXT2_FXSR    (1U << 24)
#define CPUID_EXT2_FFXSR   (1U << 25)
#define CPUID_EXT2_PDPE1GB (1U << 26)
#define CPUID_EXT2_RDTSCP  (1U << 27)
#define CPUID_EXT2_LM      (1U << 29)
#define CPUID_EXT2_3DNOWEXT (1U << 30)
#define CPUID_EXT2_3DNOW   (1U << 31)
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/* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
                                CPUID_EXT2_DE | CPUID_EXT2_PSE | \
                                CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
                                CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
                                CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
                                CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
                                CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
                                CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
                                CPUID_EXT2_MMX | CPUID_EXT2_FXSR)

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#define CPUID_EXT3_LAHF_LM (1U << 0)
#define CPUID_EXT3_CMP_LEG (1U << 1)
#define CPUID_EXT3_SVM     (1U << 2)
#define CPUID_EXT3_EXTAPIC (1U << 3)
#define CPUID_EXT3_CR8LEG  (1U << 4)
#define CPUID_EXT3_ABM     (1U << 5)
#define CPUID_EXT3_SSE4A   (1U << 6)
#define CPUID_EXT3_MISALIGNSSE (1U << 7)
#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
#define CPUID_EXT3_OSVW    (1U << 9)
#define CPUID_EXT3_IBS     (1U << 10)
#define CPUID_EXT3_XOP     (1U << 11)
#define CPUID_EXT3_SKINIT  (1U << 12)
#define CPUID_EXT3_WDT     (1U << 13)
#define CPUID_EXT3_LWP     (1U << 15)
#define CPUID_EXT3_FMA4    (1U << 16)
#define CPUID_EXT3_TCE     (1U << 17)
#define CPUID_EXT3_NODEID  (1U << 19)
#define CPUID_EXT3_TBM     (1U << 21)
#define CPUID_EXT3_TOPOEXT (1U << 22)
#define CPUID_EXT3_PERFCORE (1U << 23)
#define CPUID_EXT3_PERFNB  (1U << 24)

#define CPUID_SVM_NPT          (1U << 0)
#define CPUID_SVM_LBRV         (1U << 1)
#define CPUID_SVM_SVMLOCK      (1U << 2)
#define CPUID_SVM_NRIPSAVE     (1U << 3)
#define CPUID_SVM_TSCSCALE     (1U << 4)
#define CPUID_SVM_VMCBCLEAN    (1U << 5)
#define CPUID_SVM_FLUSHASID    (1U << 6)
#define CPUID_SVM_DECODEASSIST (1U << 7)
#define CPUID_SVM_PAUSEFILTER  (1U << 10)
#define CPUID_SVM_PFTHRESHOLD  (1U << 12)

#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
#define CPUID_7_0_EBX_BMI1     (1U << 3)
#define CPUID_7_0_EBX_HLE      (1U << 4)
#define CPUID_7_0_EBX_AVX2     (1U << 5)
#define CPUID_7_0_EBX_SMEP     (1U << 7)
#define CPUID_7_0_EBX_BMI2     (1U << 8)
#define CPUID_7_0_EBX_ERMS     (1U << 9)
#define CPUID_7_0_EBX_INVPCID  (1U << 10)
#define CPUID_7_0_EBX_RTM      (1U << 11)
#define CPUID_7_0_EBX_MPX      (1U << 14)
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#define CPUID_7_0_EBX_AVX512F  (1U << 16) /* AVX-512 Foundation */
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#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
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#define CPUID_7_0_EBX_RDSEED   (1U << 18)
#define CPUID_7_0_EBX_ADX      (1U << 19)
#define CPUID_7_0_EBX_SMAP     (1U << 20)
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#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
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#define CPUID_7_0_EBX_PCOMMIT  (1U << 22) /* Persistent Commit */
#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
#define CPUID_7_0_EBX_CLWB     (1U << 24) /* Cache Line Write Back */
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#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
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#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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#define CPUID_7_0_EBX_SHA_NI   (1U << 29) /* SHA1/SHA256 Instruction Extensions */
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#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
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#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
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#define CPUID_7_0_ECX_VBMI     (1U << 1)  /* AVX-512 Vector Byte Manipulation Instrs */
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#define CPUID_7_0_ECX_UMIP     (1U << 2)
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#define CPUID_7_0_ECX_PKU      (1U << 3)
#define CPUID_7_0_ECX_OSPKE    (1U << 4)
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#define CPUID_7_0_ECX_VBMI2    (1U << 6) /* Additional VBMI Instrs */
#define CPUID_7_0_ECX_GFNI     (1U << 8)
#define CPUID_7_0_ECX_VAES     (1U << 9)
#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
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#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
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#define CPUID_7_0_ECX_LA57     (1U << 16)
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#define CPUID_7_0_ECX_RDPID    (1U << 22)
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#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)  /* CLDEMOTE Instruction */
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#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */
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#define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */

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#define CPUID_XSAVE_XSAVEOPT   (1U << 0)
#define CPUID_XSAVE_XSAVEC     (1U << 1)
#define CPUID_XSAVE_XGETBV1    (1U << 2)
#define CPUID_XSAVE_XSAVES     (1U << 3)

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#define CPUID_6_EAX_ARAT       (1U << 2)

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/* CPUID[0x80000007].EDX flags: */
#define CPUID_APM_INVTSC       (1U << 8)

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#define CPUID_VENDOR_SZ      12

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#define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
#define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
#define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
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#define CPUID_VENDOR_INTEL "GenuineIntel"
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#define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
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#define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
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#define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
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#define CPUID_VENDOR_AMD   "AuthenticAMD"
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#define CPUID_VENDOR_VIA   "CentaurHauls"
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#define CPUID_MWAIT_IBE     (1U << 1) /* Interrupts can exit capability */
#define CPUID_MWAIT_EMX     (1U << 0) /* enumeration supported */
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/* CPUID[0xB].ECX level types */
#define CPUID_TOPOLOGY_LEVEL_INVALID  (0U << 8)
#define CPUID_TOPOLOGY_LEVEL_SMT      (1U << 8)
#define CPUID_TOPOLOGY_LEVEL_CORE     (2U << 8)

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#ifndef HYPERV_SPINLOCK_NEVER_RETRY
#define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF
#endif

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#define EXCP00_DIVZ	0
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#define EXCP01_DB	1
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#define EXCP02_NMI	2
#define EXCP03_INT3	3
#define EXCP04_INTO	4
#define EXCP05_BOUND	5
#define EXCP06_ILLOP	6
#define EXCP07_PREX	7
#define EXCP08_DBLE	8
#define EXCP09_XERR	9
#define EXCP0A_TSS	10
#define EXCP0B_NOSEG	11
#define EXCP0C_STACK	12
#define EXCP0D_GPF	13
#define EXCP0E_PAGE	14
#define EXCP10_COPR	16
#define EXCP11_ALGN	17
#define EXCP12_MCHK	18

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#define EXCP_SYSCALL    0x100 /* only happens in user only emulation
                                 for syscall instruction */
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#define EXCP_VMEXIT     0x100
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/* i386-specific interrupt pending bits.  */
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#define CPU_INTERRUPT_POLL      CPU_INTERRUPT_TGT_EXT_1
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#define CPU_INTERRUPT_SMI       CPU_INTERRUPT_TGT_EXT_2
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#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
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#define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4
#define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0
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#define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1
#define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2
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/* Use a clearer name for this.  */
#define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET
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/* Instead of computing the condition codes after each x86 instruction,
 * QEMU just stores one operand (called CC_SRC), the result
 * (called CC_DST) and the type of operation (called CC_OP). When the
 * condition codes are needed, the condition codes can be calculated
 * using this information. Condition codes are not generated if they
 * are only needed for conditional branches.
 */
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typedef enum {
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    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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    CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
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    CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
    CC_OP_MULW,
    CC_OP_MULL,
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    CC_OP_MULQ,
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    CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADDW,
    CC_OP_ADDL,
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    CC_OP_ADDQ,
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    CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_ADCW,
    CC_OP_ADCL,
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    CC_OP_ADCQ,
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    CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SUBW,
    CC_OP_SUBL,
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    CC_OP_SUBQ,
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    CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    CC_OP_SBBW,
    CC_OP_SBBL,
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    CC_OP_SBBQ,
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    CC_OP_LOGICB, /* modify all flags, CC_DST = res */
    CC_OP_LOGICW,
    CC_OP_LOGICL,
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    CC_OP_LOGICQ,
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    CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
    CC_OP_INCW,
    CC_OP_INCL,
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    CC_OP_INCQ,
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    CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
    CC_OP_DECW,
    CC_OP_DECL,
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    CC_OP_DECQ,
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    CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
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    CC_OP_SHLW,
    CC_OP_SHLL,
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    CC_OP_SHLQ,
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    CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    CC_OP_SARW,
    CC_OP_SARL,
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    CC_OP_SARQ,
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    CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
    CC_OP_BMILGW,
    CC_OP_BMILGL,
    CC_OP_BMILGQ,

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    CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest.  */
    CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest.  */
    CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest.  */

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    CC_OP_CLR, /* Z set, all other flags clear.  */
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    CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear.  */
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    CC_OP_NB,
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} CCOp;
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typedef struct SegmentCache {
    uint32_t selector;
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    target_ulong base;
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    uint32_t limit;
    uint32_t flags;
} SegmentCache;

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#define MMREG_UNION(n, bits)        \
    union n {                       \
        uint8_t  _b_##n[(bits)/8];  \
        uint16_t _w_##n[(bits)/16]; \
        uint32_t _l_##n[(bits)/32]; \
        uint64_t _q_##n[(bits)/64]; \
        float32  _s_##n[(bits)/32]; \
        float64  _d_##n[(bits)/64]; \
857 858
    }

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typedef union {
    uint8_t _b[16];
    uint16_t _w[8];
    uint32_t _l[4];
    uint64_t _q[2];
} XMMReg;

typedef union {
    uint8_t _b[32];
    uint16_t _w[16];
    uint32_t _l[8];
    uint64_t _q[4];
} YMMReg;

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typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
typedef MMREG_UNION(MMXReg, 64)  MMXReg;
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typedef struct BNDReg {
    uint64_t lb;
    uint64_t ub;
} BNDReg;

typedef struct BNDCSReg {
    uint64_t cfgu;
    uint64_t sts;
} BNDCSReg;

886 887 888 889
#define BNDCFG_ENABLE       1ULL
#define BNDCFG_BNDPRESERVE  2ULL
#define BNDCFG_BDIR_MASK    TARGET_PAGE_MASK

890
#ifdef HOST_WORDS_BIGENDIAN
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#define ZMM_B(n) _b_ZMMReg[63 - (n)]
#define ZMM_W(n) _w_ZMMReg[31 - (n)]
#define ZMM_L(n) _l_ZMMReg[15 - (n)]
#define ZMM_S(n) _s_ZMMReg[15 - (n)]
#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
#define ZMM_D(n) _d_ZMMReg[7 - (n)]

#define MMX_B(n) _b_MMXReg[7 - (n)]
#define MMX_W(n) _w_MMXReg[3 - (n)]
#define MMX_L(n) _l_MMXReg[1 - (n)]
#define MMX_S(n) _s_MMXReg[1 - (n)]
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#else
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#define ZMM_B(n) _b_ZMMReg[n]
#define ZMM_W(n) _w_ZMMReg[n]
#define ZMM_L(n) _l_ZMMReg[n]
#define ZMM_S(n) _s_ZMMReg[n]
#define ZMM_Q(n) _q_ZMMReg[n]
#define ZMM_D(n) _d_ZMMReg[n]

#define MMX_B(n) _b_MMXReg[n]
#define MMX_W(n) _w_MMXReg[n]
#define MMX_L(n) _l_MMXReg[n]
#define MMX_S(n) _s_MMXReg[n]
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#endif
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#define MMX_Q(n) _q_MMXReg[n]
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typedef union {
918
    floatx80 d __attribute__((aligned(16)));
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    MMXReg mmx;
} FPReg;

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typedef struct {
    uint64_t base;
    uint64_t mask;
} MTRRVar;

927 928 929
#define CPU_NB_REGS64 16
#define CPU_NB_REGS32 8

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#ifdef TARGET_X86_64
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#define CPU_NB_REGS CPU_NB_REGS64
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#else
933
#define CPU_NB_REGS CPU_NB_REGS32
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#endif

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#define MAX_FIXED_COUNTERS 3
#define MAX_GP_COUNTERS    (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)

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#define NB_MMU_MODES 3
940
#define TARGET_INSN_START_EXTRA_WORDS 1
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#define NB_OPMASK_REGS 8

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/* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
 * that APIC ID hasn't been set yet
 */
#define UNASSIGNED_APIC_ID 0xFFFFFFFF

949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968
typedef union X86LegacyXSaveArea {
    struct {
        uint16_t fcw;
        uint16_t fsw;
        uint8_t ftw;
        uint8_t reserved;
        uint16_t fpop;
        uint64_t fpip;
        uint64_t fpdp;
        uint32_t mxcsr;
        uint32_t mxcsr_mask;
        FPReg fpregs[8];
        uint8_t xmm_regs[16][16];
    };
    uint8_t data[512];
} X86LegacyXSaveArea;

typedef struct X86XSaveHeader {
    uint64_t xstate_bv;
    uint64_t xcomp_bv;
969 970
    uint64_t reserve0;
    uint8_t reserved[40];
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} X86XSaveHeader;

/* Ext. save area 2: AVX State */
typedef struct XSaveAVX {
    uint8_t ymmh[16][16];
} XSaveAVX;

/* Ext. save area 3: BNDREG */
typedef struct XSaveBNDREG {
    BNDReg bnd_regs[4];
} XSaveBNDREG;

/* Ext. save area 4: BNDCSR */
typedef union XSaveBNDCSR {
    BNDCSReg bndcsr;
    uint8_t data[64];
} XSaveBNDCSR;

/* Ext. save area 5: Opmask */
typedef struct XSaveOpmask {
    uint64_t opmask_regs[NB_OPMASK_REGS];
} XSaveOpmask;

/* Ext. save area 6: ZMM_Hi256 */
typedef struct XSaveZMM_Hi256 {
    uint8_t zmm_hi256[16][32];
} XSaveZMM_Hi256;

/* Ext. save area 7: Hi16_ZMM */
typedef struct XSaveHi16_ZMM {
    uint8_t hi16_zmm[16][64];
} XSaveHi16_ZMM;

/* Ext. save area 9: PKRU state */
typedef struct XSavePKRU {
    uint32_t pkru;
    uint32_t padding;
} XSavePKRU;

typedef struct X86XSaveArea {
    X86LegacyXSaveArea legacy;
    X86XSaveHeader header;

    /* Extended save areas: */

    /* AVX State: */
    XSaveAVX avx_state;
    uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
    /* MPX State: */
    XSaveBNDREG bndreg_state;
    XSaveBNDCSR bndcsr_state;
    /* AVX-512 State: */
    XSaveOpmask opmask_state;
    XSaveZMM_Hi256 zmm_hi256_state;
    XSaveHi16_ZMM hi16_zmm_state;
    /* PKRU State: */
    XSavePKRU pkru_state;
} X86XSaveArea;

QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);

1045 1046 1047 1048 1049
typedef enum TPRAccess {
    TPR_ACCESS_READ,
    TPR_ACCESS_WRITE,
} TPRAccess;

1050 1051 1052
/* Cache information data structures: */

enum CacheType {
1053 1054
    DATA_CACHE,
    INSTRUCTION_CACHE,
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101
    UNIFIED_CACHE
};

typedef struct CPUCacheInfo {
    enum CacheType type;
    uint8_t level;
    /* Size in bytes */
    uint32_t size;
    /* Line size, in bytes */
    uint16_t line_size;
    /*
     * Associativity.
     * Note: representation of fully-associative caches is not implemented
     */
    uint8_t associativity;
    /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
    uint8_t partitions;
    /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
    uint32_t sets;
    /*
     * Lines per tag.
     * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
     * (Is this synonym to @partitions?)
     */
    uint8_t lines_per_tag;

    /* Self-initializing cache */
    bool self_init;
    /*
     * WBINVD/INVD is not guaranteed to act upon lower level caches of
     * non-originating threads sharing this cache.
     * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
     */
    bool no_invd_sharing;
    /*
     * Cache is inclusive of lower cache levels.
     * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
     */
    bool inclusive;
    /*
     * A complex function is used to index the cache, potentially using all
     * address bits.  CPUID[4].EDX[bit 2].
     */
    bool complex_indexing;
} CPUCacheInfo;


1102
typedef struct CPUCaches {
1103 1104 1105 1106
        CPUCacheInfo *l1d_cache;
        CPUCacheInfo *l1i_cache;
        CPUCacheInfo *l2_cache;
        CPUCacheInfo *l3_cache;
1107
} CPUCaches;
1108

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typedef struct CPUX86State {
    /* standard registers */
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    target_ulong regs[CPU_NB_REGS];
    target_ulong eip;
    target_ulong eflags; /* eflags register. During CPU emulation, CC
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                        flags and DF are set to zero because they are
                        stored elsewhere */

    /* emulator internal eflags handling */
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    target_ulong cc_dst;
1119 1120
    target_ulong cc_src;
    target_ulong cc_src2;
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    uint32_t cc_op;
    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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    uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
                        are known at translation time. */
    uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
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    /* segments */
    SegmentCache segs[6]; /* selector values */
    SegmentCache ldt;
    SegmentCache tr;
    SegmentCache gdt; /* only base and limit are used */
    SegmentCache idt; /* only base and limit are used */

1134
    target_ulong cr[5]; /* NOTE: cr1 is unused */
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    int32_t a20_mask;
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1137 1138 1139
    BNDReg bnd_regs[4];
    BNDCSReg bndcs_regs;
    uint64_t msr_bndcfgs;
1140
    uint64_t efer;
1141

1142 1143 1144
    /* Beginning of state preserved by INIT (dummy marker).  */
    struct {} start_init_save;

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    /* FPU state */
    unsigned int fpstt; /* top of stack index */
1147
    uint16_t fpus;
1148
    uint16_t fpuc;
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    uint8_t fptags[8];   /* 0 = valid, 1 = empty */
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    FPReg fpregs[8];
1151 1152 1153 1154
    /* KVM-only so far */
    uint16_t fpop;
    uint64_t fpip;
    uint64_t fpdp;
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    /* emulator internal variables */
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    float_status fp_status;
1158
    floatx80 ft0;
1159

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    float_status mmx_status; /* for 3DNow! float ops */
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    float_status sse_status;
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    uint32_t mxcsr;
1163 1164
    ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
    ZMMReg xmm_t0;
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    MMXReg mmx_t0;
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    XMMReg ymmh_regs[CPU_NB_REGS];

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    uint64_t opmask_regs[NB_OPMASK_REGS];
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    YMMReg zmmh_regs[CPU_NB_REGS];
    ZMMReg hi16_zmm_regs[CPU_NB_REGS];
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    /* sysenter registers */
    uint32_t sysenter_cs;
1175 1176
    target_ulong sysenter_esp;
    target_ulong sysenter_eip;
1177
    uint64_t star;
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    uint64_t vm_hsave;
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#ifdef TARGET_X86_64
    target_ulong lstar;
    target_ulong cstar;
    target_ulong fmask;
    target_ulong kernelgsbase;
#endif
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    uint64_t tsc;
1189
    uint64_t tsc_adjust;
1190
    uint64_t tsc_deadline;
1191 1192 1193
    uint64_t tsc_aux;

    uint64_t xcr0;
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1195
    uint64_t mcg_status;
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    uint64_t msr_ia32_misc_enable;
1197
    uint64_t msr_ia32_feature_control;
1198

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    uint64_t msr_fixed_ctr_ctrl;
    uint64_t msr_global_ctrl;
    uint64_t msr_global_status;
    uint64_t msr_global_ovf_ctrl;
    uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
    uint64_t msr_gp_counters[MAX_GP_COUNTERS];
    uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1206 1207 1208

    uint64_t pat;
    uint32_t smbase;
1209
    uint64_t msr_smi_count;
1210

1211 1212
    uint32_t pkru;

1213
    uint64_t spec_ctrl;
1214
    uint64_t virt_ssbd;
1215

1216 1217 1218 1219 1220 1221 1222 1223 1224
    /* End of state preserved by INIT (dummy marker).  */
    struct {} end_init_save;

    uint64_t system_time_msr;
    uint64_t wall_clock_msr;
    uint64_t steal_time_msr;
    uint64_t async_pf_en_msr;
    uint64_t pv_eoi_en_msr;

1225
    /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1226 1227
    uint64_t msr_hv_hypercall;
    uint64_t msr_hv_guest_os_id;
1228
    uint64_t msr_hv_tsc;
1229 1230 1231

    /* Per-VCPU HV MSRs */
    uint64_t msr_hv_vapic;
1232
    uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1233
    uint64_t msr_hv_runtime;
1234 1235 1236
    uint64_t msr_hv_synic_control;
    uint64_t msr_hv_synic_evt_page;
    uint64_t msr_hv_synic_msg_page;
1237 1238 1239
    uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
    uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
    uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1240 1241 1242
    uint64_t msr_hv_reenlightenment_control;
    uint64_t msr_hv_tsc_emulation_control;
    uint64_t msr_hv_tsc_emulation_status;
1243

1244 1245 1246 1247 1248 1249 1250
    uint64_t msr_rtit_ctrl;
    uint64_t msr_rtit_status;
    uint64_t msr_rtit_output_base;
    uint64_t msr_rtit_output_mask;
    uint64_t msr_rtit_cr3_match;
    uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];

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    /* exception/interrupt handling */
    int error_code;
    int exception_is_int;
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    target_ulong exception_next_eip;
1255
    target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1256
    union {
1257
        struct CPUBreakpoint *cpu_breakpoint[4];
1258
        struct CPUWatchpoint *cpu_watchpoint[4];
1259
    }; /* break/watchpoints for dr[0..3] */
1260
    int old_exception;  /* exception in flight */
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1262 1263 1264 1265 1266 1267 1268 1269
    uint64_t vm_vmcb;
    uint64_t tsc_offset;
    uint64_t intercept;
    uint16_t intercept_cr_read;
    uint16_t intercept_cr_write;
    uint16_t intercept_dr_read;
    uint16_t intercept_dr_write;
    uint32_t intercept_exceptions;
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    uint64_t nested_cr3;
    uint32_t nested_pg_mode;
1272 1273
    uint8_t v_tpr;

1274 1275 1276 1277
    /* KVM states, automatically cleared on reset */
    uint8_t nmi_injected;
    uint8_t nmi_pending;

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    uintptr_t retaddr;

1280 1281 1282
    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

1283
    CPU_COMMON
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1285
    /* Fields after CPU_COMMON are preserved across CPU reset. */
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    /* processor features (e.g. for CPUID insn) */
1288 1289 1290 1291 1292 1293
    /* Minimum level/xlevel/xlevel2, based on CPU model + features */
    uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
    /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
    uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
    /* Actual level/xlevel/xlevel2 value: */
    uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
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    uint32_t cpuid_vendor1;
    uint32_t cpuid_vendor2;
    uint32_t cpuid_vendor3;
    uint32_t cpuid_version;
1298
    FeatureWordArray features;
1299 1300
    /* Features that were explicitly enabled/disabled */
    FeatureWordArray user_features;
1301
    uint32_t cpuid_model[12];
1302 1303 1304 1305 1306
    /* Cache information for CPUID.  When legacy-cache=on, the cache data
     * on each CPUID leaf will be different, because we keep compatibility
     * with old QEMU versions.
     */
    CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1307

1308 1309 1310
    /* MTRRs */
    uint64_t mtrr_fixed[11];
    uint64_t mtrr_deftype;
1311
    MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1312

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    /* For KVM */
1314
    uint32_t mp_state;
1315
    int32_t exception_injected;
1316
    int32_t interrupt_injected;
1317 1318
    uint8_t soft_interrupt;
    uint8_t has_error_code;
1319
    uint32_t ins_len;
1320
    uint32_t sipi_vector;
1321
    bool tsc_valid;
1322
    int64_t tsc_khz;
1323
    int64_t user_tsc_khz; /* for sanity check only */
1324
    void *kvm_xsave_buf;
1325 1326 1327
#if defined(CONFIG_HVF)
    HVFX86EmulatorState *hvf_emul;
#endif
1328

1329 1330
    uint64_t mcg_cap;
    uint64_t mcg_ctl;
1331
    uint64_t mcg_ext_ctl;
1332
    uint64_t mce_banks[MCE_BANKS_DEF*4];
1333
    uint64_t xstate_bv;
1334 1335 1336 1337 1338

    /* vmstate */
    uint16_t fpus_vmstate;
    uint16_t fptag_vmstate;
    uint16_t fpregs_format_vmstate;
1339

1340
    uint64_t xss;
1341 1342

    TPRAccess tpr_access_type;
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} CPUX86State;

1345 1346
struct kvm_msrs;

1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373
/**
 * X86CPU:
 * @env: #CPUX86State
 * @migratable: If set, only migratable flags will be accepted when "enforce"
 * mode is used, and only migratable flags will be included in the "host"
 * CPU model.
 *
 * An x86 CPU.
 */
struct X86CPU {
    /*< private >*/
    CPUState parent_obj;
    /*< public >*/

    CPUX86State env;

    bool hyperv_vapic;
    bool hyperv_relaxed_timing;
    int hyperv_spinlock_attempts;
    char *hyperv_vendor_id;
    bool hyperv_time;
    bool hyperv_crash;
    bool hyperv_reset;
    bool hyperv_vpindex;
    bool hyperv_runtime;
    bool hyperv_synic;
    bool hyperv_stimer;
1374
    bool hyperv_frequencies;
1375
    bool hyperv_reenlightenment;
1376
    bool hyperv_tlbflush;
1377 1378 1379
    bool check_cpuid;
    bool enforce_cpuid;
    bool expose_kvm;
1380
    bool expose_tcg;
1381
    bool migratable;
1382
    bool migrate_smi_count;
1383
    bool max_features; /* Enable all supported features automatically */
1384
    uint32_t apic_id;
1385

1386 1387 1388 1389
    /* Enables publishing of TSC increment and Local APIC bus frequencies to
     * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
    bool vmware_cpuid_freq;

1390 1391 1392
    /* if true the CPUID code directly forward host cache leaves to the guest */
    bool cache_info_passthrough;

1393 1394 1395 1396 1397 1398 1399 1400 1401
    /* if true the CPUID code directly forwards
     * host monitor/mwait leaves to the guest */
    struct {
        uint32_t eax;
        uint32_t ebx;
        uint32_t ecx;
        uint32_t edx;
    } mwait;

1402 1403 1404 1405 1406 1407 1408 1409 1410 1411
    /* Features that were filtered out because of missing host capabilities */
    uint32_t filtered_features[FEATURE_WORDS];

    /* Enable PMU CPUID bits. This can't be enabled by default yet because
     * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
     * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
     * capabilities) directly to the guest.
     */
    bool enable_pmu;

1412 1413 1414 1415 1416 1417
    /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
     * disabled by default to avoid breaking migration between QEMU with
     * different LMCE configurations.
     */
    bool enable_lmce;

1418 1419 1420 1421 1422 1423
    /* Compatibility bits for old machine types.
     * If true present virtual l3 cache for VM, the vcpus in the same virtual
     * socket share an virtual l3 cache.
     */
    bool enable_l3_cache;

1424 1425 1426 1427 1428
    /* Compatibility bits for old machine types.
     * If true present the old cache topology information
     */
    bool legacy_cache;

1429 1430 1431
    /* Compatibility bits for old machine types: */
    bool enable_cpuid_0xb;

1432 1433 1434
    /* Enable auto level-increase for all CPUID leaves */
    bool full_cpuid_auto_level;

1435 1436 1437
    /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
    bool fill_mtrr_mask;

1438 1439 1440
    /* if true override the phys_bits value with a value read from the host */
    bool host_phys_bits;

1441 1442 1443
    /* Stop SMI delivery for migration compatibility with old machines */
    bool kvm_no_smi_migration;

1444 1445 1446
    /* Number of physical address bits supported */
    uint32_t phys_bits;

1447 1448 1449 1450 1451
    /* in order to simplify APIC support, we leave this pointer to the
       user */
    struct DeviceState *apic_state;
    struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
    Notifier machine_done;
1452 1453

    struct kvm_msrs *kvm_msr_buf;
1454

1455
    int32_t node_id; /* NUMA node this CPU belongs to */
1456 1457 1458
    int32_t socket_id;
    int32_t core_id;
    int32_t thread_id;
1459 1460

    int32_t hv_max_vps;
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504
};

static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
{
    return container_of(env, X86CPU, env);
}

#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))

#define ENV_OFFSET offsetof(X86CPU, env)

#ifndef CONFIG_USER_ONLY
extern struct VMStateDescription vmstate_x86_cpu;
#endif

/**
 * x86_cpu_do_interrupt:
 * @cpu: vCPU the interrupt is to be handled by.
 */
void x86_cpu_do_interrupt(CPUState *cpu);
bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);

int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
                             int cpuid, void *opaque);
int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
                             int cpuid, void *opaque);
int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
                                 void *opaque);
int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
                                 void *opaque);

void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
                                Error **errp);

void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
                        int flags);

hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

void x86_cpu_exec_enter(CPUState *cpu);
void x86_cpu_exec_exit(CPUState *cpu);
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void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1507
int cpu_x86_support_mca_broadcast(CPUX86State *env);
1508

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1509
int cpu_get_pic_interrupt(CPUX86State *s);
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1510 1511
/* MSDOS compatibility mode FPU exception support */
void cpu_set_ferr(CPUX86State *s);
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1512 1513 1514

/* this function must always be used to load data in the segment
   cache: it synchronizes the hflags with the segment cache values */
1515
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
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                                          int seg_reg, unsigned int selector,
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1517
                                          target_ulong base,
1518
                                          unsigned int limit,
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1519 1520 1521 1522
                                          unsigned int flags)
{
    SegmentCache *sc;
    unsigned int new_hflags;
1523

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1524 1525 1526 1527 1528 1529 1530
    sc = &env->segs[seg_reg];
    sc->selector = selector;
    sc->base = base;
    sc->limit = limit;
    sc->flags = flags;

    /* update the hidden flags */
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1531 1532 1533 1534 1535 1536 1537
    {
        if (seg_reg == R_CS) {
#ifdef TARGET_X86_64
            if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
                /* long mode */
                env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
                env->hflags &= ~(HF_ADDSEG_MASK);
1538
            } else
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1539 1540 1541 1542 1543 1544 1545 1546
#endif
            {
                /* legacy / compatibility case */
                new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
                    >> (DESC_B_SHIFT - HF_CS32_SHIFT);
                env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
                    new_hflags;
            }
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Paolo Bonzini 已提交
1547 1548 1549
        }
        if (seg_reg == R_SS) {
            int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1550 1551 1552 1553
#if HF_CPL_MASK != 3
#error HF_CPL_MASK is hardcoded
#endif
            env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
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1554 1555 1556 1557 1558
        }
        new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
            >> (DESC_B_SHIFT - HF_SS32_SHIFT);
        if (env->hflags & HF_CS64_MASK) {
            /* zero base assumed for DS, ES and SS in long mode */
1559
        } else if (!(env->cr[0] & CR0_PE_MASK) ||
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1560 1561
                   (env->eflags & VM_MASK) ||
                   !(env->hflags & HF_CS32_MASK)) {
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1562 1563 1564 1565 1566 1567 1568
            /* XXX: try to avoid this test. The problem comes from the
               fact that is real mode or vm86 mode we only modify the
               'base' and 'selector' fields of the segment cache to go
               faster. A solution may be to force addseg to one in
               translate-i386.c. */
            new_hflags |= HF_ADDSEG_MASK;
        } else {
1569
            new_hflags |= ((env->segs[R_DS].base |
B
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1570
                            env->segs[R_ES].base |
1571
                            env->segs[R_SS].base) != 0) <<
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1572 1573
                HF_ADDSEG_SHIFT;
        }
1574
        env->hflags = (env->hflags &
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1575
                       ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
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1576 1577 1578
    }
}

1579
static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1580
                                               uint8_t sipi_vector)
1581
{
1582
    CPUState *cs = CPU(cpu);
1583 1584
    CPUX86State *env = &cpu->env;

1585 1586 1587 1588 1589
    env->eip = 0;
    cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
                           sipi_vector << 12,
                           env->segs[R_CS].limit,
                           env->segs[R_CS].flags);
1590
    cs->halted = 0;
1591 1592
}

1593 1594 1595 1596
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
                            target_ulong *base, unsigned int *limit,
                            unsigned int *flags);

B
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1597
/* op_helper.c */
1598 1599
/* used for debug or cpu save/restore */

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1600
/* cpu-exec.c */
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1601 1602 1603
/* the following helpers are only usable in user mode simulation as
   they can trigger unexpected exceptions */
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1604 1605
void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1606 1607
void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
B
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1608 1609 1610 1611

/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
1612
int cpu_x86_signal_handler(int host_signum, void *pinfo,
B
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1613
                           void *puc);
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1614

1615
/* cpu.c */
1616 1617 1618
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
                   uint32_t *eax, uint32_t *ebx,
                   uint32_t *ecx, uint32_t *edx);
1619
void cpu_clear_apic_feature(CPUX86State *env);
1620 1621
void host_cpuid(uint32_t function, uint32_t count,
                uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1622
void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1623

B
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1624
/* helper.c */
1625
int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, int size,
1626
                             int is_write, int mmu_idx);
1627
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
B
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1628

1629
#ifndef CONFIG_USER_ONLY
1630 1631 1632 1633 1634 1635 1636 1637 1638 1639
static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
{
    return !!attrs.secure;
}

static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
{
    return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
}

1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650
uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
#endif

1651
void breakpoint_handler(CPUState *cs);
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/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1657
void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
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1658 1659 1660

/* hw/pc.c */
uint64_t cpu_get_tsc(CPUX86State *env);
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B
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1662
#define TARGET_PAGE_BITS 12
1663

1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674
#ifdef TARGET_X86_64
#define TARGET_PHYS_ADDR_SPACE_BITS 52
/* ??? This is really 48 bits, sign-extended, but the only thing
   accessible to userland with bit 48 set is the VSYSCALL, and that
   is handled via other mechanisms.  */
#define TARGET_VIRT_ADDR_SPACE_BITS 47
#else
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif

1675 1676 1677
/* XXX: This value should match the one returned by CPUID
 * and in exec.c */
# if defined(TARGET_X86_64)
1678
# define TCG_PHYS_ADDR_BITS 40
1679
# else
1680
# define TCG_PHYS_ADDR_BITS 36
1681 1682
# endif

1683 1684
#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)

1685 1686
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1687
#define CPU_RESOLVING_TYPE TYPE_X86_CPU
1688 1689 1690 1691 1692 1693 1694

#ifdef TARGET_X86_64
#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
#else
#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
#endif

1695
#define cpu_signal_handler cpu_x86_signal_handler
P
Peter Maydell 已提交
1696
#define cpu_list x86_cpu_list
1697

1698
/* MMU modes definitions */
1699
#define MMU_MODE0_SUFFIX _ksmap
1700
#define MMU_MODE1_SUFFIX _user
1701
#define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1702
#define MMU_KSMAP_IDX   0
H
H. Peter Anvin 已提交
1703
#define MMU_USER_IDX    1
1704
#define MMU_KNOSMAP_IDX 2
1705
static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1706
{
H
H. Peter Anvin 已提交
1707
    return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1708
        (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1709 1710 1711 1712 1713 1714 1715 1716
        ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
}

static inline int cpu_mmu_index_kernel(CPUX86State *env)
{
    return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
        ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
        ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1717 1718
}

1719 1720 1721 1722
#define CC_DST  (env->cc_dst)
#define CC_SRC  (env->cc_src)
#define CC_SRC2 (env->cc_src2)
#define CC_OP   (env->cc_op)
1723

1724 1725 1726 1727 1728 1729 1730 1731 1732 1733
/* n must be a constant to be efficient */
static inline target_long lshift(target_long x, int n)
{
    if (n >= 0) {
        return x << n;
    } else {
        return x >> (-n);
    }
}

1734 1735 1736 1737 1738 1739
/* float macros */
#define FT0    (env->ft0)
#define ST0    (env->fpregs[env->fpstt].d)
#define ST(n)  (env->fpregs[(env->fpstt + (n)) & 7].d)
#define ST1    ST(1)

B
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1740
/* translate.c */
1741
void tcg_x86_init(void);
1742

1743
#include "exec/cpu-all.h"
T
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1744 1745
#include "svm.h"

1746
#if !defined(CONFIG_USER_ONLY)
P
Paolo Bonzini 已提交
1747
#include "hw/i386/apic.h"
1748 1749
#endif

1750
static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1751
                                        target_ulong *cs_base, uint32_t *flags)
1752 1753 1754
{
    *cs_base = env->segs[R_CS].base;
    *pc = *cs_base + env->eip;
J
Jan Kiszka 已提交
1755
    *flags = env->hflags |
H
H. Peter Anvin 已提交
1756
        (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1757 1758
}

1759 1760
void do_cpu_init(X86CPU *cpu);
void do_cpu_sipi(X86CPU *cpu);
J
Jan Kiszka 已提交
1761

1762 1763 1764
#define MCE_INJECT_BROADCAST    1
#define MCE_INJECT_UNCOND_AO    2

1765
void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1766
                        uint64_t status, uint64_t mcg_status, uint64_t addr,
1767
                        uint64_t misc, int flags);
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1768

B
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1769
/* excp_helper.c */
B
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1770
void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1771 1772
void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
                                      uintptr_t retaddr);
B
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1773 1774
void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
                                       int error_code);
1775 1776
void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
                                          int error_code, uintptr_t retaddr);
B
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1777 1778 1779
void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
                                   int error_code, int next_eip_addend);

1780 1781 1782 1783 1784 1785
/* cc_helper.c */
extern const uint8_t parity_table[256];
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);

static inline uint32_t cpu_compute_eflags(CPUX86State *env)
{
1786 1787 1788 1789 1790
    uint32_t eflags = env->eflags;
    if (tcg_enabled()) {
        eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
    }
    return eflags;
1791 1792
}

1793 1794 1795
/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
 * after generating a call to a helper that uses this.
 */
1796 1797 1798 1799
static inline void cpu_load_eflags(CPUX86State *env, int eflags,
                                   int update_mask)
{
    CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1800
    CC_OP = CC_OP_EFLAGS;
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1801
    env->df = 1 - (2 * ((eflags >> 10) & 1));
1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819
    env->eflags = (env->eflags & ~update_mask) |
        (eflags & update_mask) | 0x2;
}

/* load efer and update the corresponding hflags. XXX: do consistency
   checks with cpuid bits? */
static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
{
    env->efer = val;
    env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
    if (env->efer & MSR_EFER_LMA) {
        env->hflags |= HF_LMA_MASK;
    }
    if (env->efer & MSR_EFER_SVME) {
        env->hflags |= HF_SVME_MASK;
    }
}

1820 1821 1822 1823 1824
static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
{
    return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
}

1825 1826 1827 1828 1829 1830 1831 1832 1833
static inline int32_t x86_get_a20_mask(CPUX86State *env)
{
    if (env->hflags & HF_SMM_MASK) {
        return -1;
    } else {
        return env->a20_mask;
    }
}

1834
/* fpu_helper.c */
1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852
void update_fp_status(CPUX86State *env);
void update_mxcsr_status(CPUX86State *env);

static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
{
    env->mxcsr = mxcsr;
    if (tcg_enabled()) {
        update_mxcsr_status(env);
    }
}

static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
{
     env->fpuc = fpuc;
     if (tcg_enabled()) {
        update_fp_status(env);
     }
}
1853

K
KONRAD Frederic 已提交
1854 1855 1856
/* mem_helper.c */
void helper_lock_init(void);

B
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1857 1858
/* svm_helper.c */
void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1859
                                   uint64_t param, uintptr_t retaddr);
1860 1861
void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
                              uint64_t exit_info_1, uintptr_t retaddr);
1862
void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
B
Blue Swirl 已提交
1863

1864
/* seg_helper.c */
B
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1865
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1866

1867
/* smm_helper.c */
1868
void do_smm_enter(X86CPU *cpu);
1869

1870
/* apic.c */
1871
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1872 1873 1874
void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
                                   TPRAccess access);

1875

1876 1877 1878 1879 1880
/* Change the value of a KVM-specific default
 *
 * If value is NULL, no default will be set and the original
 * value from the CPU model table will be kept.
 *
S
Stefan Weil 已提交
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 * It is valid to call this function only for properties that
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 * are already present in the kvm_default_props table.
 */
void x86_cpu_change_kvm_default(const char *prop, const char *value);
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/* mpx_helper.c */
void cpu_sync_bndcs_hflags(CPUX86State *env);
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/* Return name of 32-bit register, from a R_* constant */
const char *get_register_name_32(unsigned int reg);

1892
void enable_compat_apic_id_mode(void);
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#define APIC_DEFAULT_ADDRESS 0xfee00000
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#define APIC_SPACE_SIZE      0x100000
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void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
                                   fprintf_function cpu_fprintf, int flags);

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/* cpu.c */
bool cpu_is_bsp(X86CPU *cpu);

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void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
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void x86_update_hflags(CPUX86State* env);

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#endif /* I386_CPU_H */