1. 17 12月, 2019 27 次提交
  2. 16 12月, 2019 4 次提交
  3. 14 12月, 2019 6 次提交
  4. 13 12月, 2019 3 次提交
    • H
      conf: create memory bandwidth monitor. · 40a070ae
      Huaqiang 提交于
      Following domain configuration changes create two memory bandwidth
      monitors: one is monitoring the bandwidth consumed by vCPU 0,
      another is for vCPU 5.
      
      ```
                     <cputune>
                       <memorytune vcpus='0-4'>
                         <node id='0' bandwidth='20'/>
                         <node id='1' bandwidth='30'/>
             +           <monitor vcpus='0'/>
                       </memorytune>
             +         <memorytune vcpus='5'>
             +           <monitor vcpus='5'/>
             +         </memorytune>
      
                     </cputune>
          ```
      Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
      Signed-off-by: NHuaqiang <huaqiang.wang@intel.com>
      40a070ae
    • H
      cachetune schema: a looser check for the order of <cache> and <monitor> element · 1d0c3c3a
      Huaqiang 提交于
      Originally, inside <cputune/cachetune>, it requires the <cache> element to
      be in the position before <monitor>, and following configuration is not
      permitted by schema, but it is better to let it be valid.
      
        <cputune>
          <cachetune vcpus='0-1'>
            <monitor level='3' vcpus='0-1'/>
                  ^
                  |__ Not permitted originally because it is in the place
                      before <cache> element.
      
            <cache id='0' level='3' type='both' size='3' unit='MiB'/>
            <cache id='1' level='3' type='both' size='3' unit='MiB'/>
          </cachetune>
          ...
        </cputune>
      
      And, let schema do more strict check by identifying following configuration to
      be invalid, due to <cachetune> should contain at least one <cache> or <monitor>
      element.
      
        <cputune>
          <cachetune vcpus='0-1'>
              ^
              |__ a <cachetune> SHOULD contain at least one <cache> or <monitor>
      
          </cachetune>
          ...
        </cputune>
      Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
      Signed-off-by: NHuaqiang <huaqiang.wang@intel.com>
      1d0c3c3a
    • H
      conf: showing cache/memoryBW monitor features in capabilities · d0431255
      Huaqiang 提交于
      We learned that the hardware features of CAT, CMT, MBA and MBM
      are orthogonal ones, if CAT or MBA is not supported in system,
      but CMT or MBM are supported, then the cache monitor or
      memoryBW monitor features may not be correctly displayed in
      host capabilities through command 'virsh capabilites'.
      
      Showing the cache/memoryBW monitor capabilities even there is
      no support of cache allocation or memoryBW allocation features.
      Reviewed-by: NDaniel P. Berrangé <berrange@redhat.com>
      Signed-off-by: NHuaqiang <huaqiang.wang@intel.com>
      d0431255