1. 15 6月, 2016 2 次提交
  2. 14 6月, 2016 3 次提交
  3. 09 6月, 2016 5 次提交
  4. 26 5月, 2016 1 次提交
    • L
      conf: permit auto-assignment of controller indexes · 4d100c7a
      Laine Stump 提交于
      Hand-entering indexes for 20 PCI controllers is not as tedious as
      manually determining and entering their PCI addresses, but it's still
      annoying, and the algorithm for determining the proper index is
      incredibly simple (in all cases except one) - just pick the lowest
      unused index.
      
      The one exception is USB2 controllers because multiple controllers in
      the same group have the same index. For these we look to see if 1) the
      most recently added USB controller is also a USB2 controller, and 2)
      the group *that* controller belongs to doesn't yet have a controller
      of the exact model we're just now adding - if both are true, the new
      controller gets the same index, but in all other cases we just assign
      the lowest unused index.
      
      With this patch in place and combined with the automatic PCI address
      assignment, we can define a PCIe switch with several ports like this:
      
        <controller type='pci' model='pcie-root-port'/>
        <controller type='pci' model='pcie-switch-upstream-port'/>
        <controller type='pci' model='pcie-switch-downstream-port'/>
        <controller type='pci' model='pcie-switch-downstream-port'/>
        <controller type='pci' model='pcie-switch-downstream-port'/>
        <controller type='pci' model='pcie-switch-downstream-port'/>
        <controller type='pci' model='pcie-switch-downstream-port'/>
        ...
      
      These will each get a unique index, and PCI addresses that connect
      them together appropriately with no pesky numbers required.
      4d100c7a
  5. 25 5月, 2016 1 次提交
  6. 21 5月, 2016 1 次提交
    • L
      conf: allow type='pci' addresses with no address attributes specified · 8f578716
      Laine Stump 提交于
      Prior to this, <address type='pci'/> wasn't allowed when parsing
      (domain+bus+slot+function needed to be a "valid" PCI address, meaning
      that at least one of domain/bus/slot had to be non-0), the RNG
      required bus to be specified, and if type was set to PCI when
      formatting, domain+bus+slot+function would always be output.
      
      This makes all the address attributes optional during parse and RNG
      validation, and suppresses domain+bus+slot+function if domain+bus+slot
      are all 0 (NB: if d+b+s are all 0, any value for function is
      nonsensical as that will never happen in the real world, and after
      the next patch we will always assign a real working address to any
      empty PCI address before it is ever output to anywhere).
      
      Note that explicitly setting all attributes to 0 is equivalent to
      setting none of them, which is okay, since 0000:00:00 is reserved in
      any PCI bus setup, and can't be used anyway.
      8f578716
  7. 20 5月, 2016 1 次提交
  8. 17 5月, 2016 2 次提交
  9. 11 5月, 2016 3 次提交
    • J
      docs: Fix disk "volume" description · 70ac2461
      John Ferlan 提交于
      Missing a close single quote and a 'be' before used.
      70ac2461
    • L
      docs: fix version number in vlan tagging documentation · f21017ab
      Laine Stump 提交于
      My brain suffered a time warp and I got the version number wrong.
      f21017ab
    • L
      util: set vlan tag for macvtap passthrough mode on SRIOV VFs · 75db9997
      Laine Stump 提交于
      SRIOV VFs used in macvtap passthrough mode can take advantage of the
      SRIOV card's transparent vlan tagging. All the code was there to set
      the vlan tag, and it has been used for SRIOV VFs used for hostdev
      interfaces for several years, but for some reason, the vlan tag for
      macvtap passthrough devices was stubbed out with a -1.
      
      This patch moves a bit of common validation down to a lower level
      (virNetDevReplaceNetConfig()) so it is shared by hostdev and macvtap
      modes, and updates the macvtap caller to actually send the vlan config
      instead of -1.
      75db9997
  10. 04 5月, 2016 3 次提交
  11. 03 5月, 2016 1 次提交
  12. 02 5月, 2016 2 次提交
  13. 30 4月, 2016 1 次提交
    • L
      Revert "libvirt domain xml allow to set peer address" · 1d14b13f
      Laine Stump 提交于
      This reverts commit 690969af, which
      added the domain config parts to support a "peer" attribute in domain
      interface <ip> elements.
      
      It's being removed temporarily for the release of libvirt 1.3.4
      because the feature doesn't work, and there are concerns that it may
      need to be modified in an externally visible manner which could create
      backward compatibility problems.
      1d14b13f
  14. 26 4月, 2016 1 次提交
  15. 25 4月, 2016 1 次提交
    • A
      docs: Fix some formatting oddities · 7867c579
      Andrea Bolognani 提交于
      When describing attributes and elements, we mostly stick to
      a certain pattern; however, there are a few cases when the
      information is not presented in the usual way.
      
      Since there doesn't seem to be any reason not to follow the
      tried and true formula, rework those bits to fit the rest of
      the documentation.
      7867c579
  16. 22 4月, 2016 1 次提交
  17. 21 4月, 2016 1 次提交
  18. 20 4月, 2016 1 次提交
  19. 15 4月, 2016 4 次提交
    • L
      conf: new pci controller model pcie-expander-bus · bc07251f
      Laine Stump 提交于
      This controller provides a single PCIe port on a new root. It is
      similar to pci-expander-bus, intended to provide a bus that can be
      associated with a guest-identifiable NUMA node, but is for
      machinetypes with PCIe rather than PCI (e.g. q35-based machinetypes).
      
      Aside from PCIe vs. PCI, the other main difference is that a
      pci-expander-bus has a companion pci-bridge that is automatically
      attached along with it, but pcie-expander-bus has only a single port,
      and that port will only connect to a pcie-root-port, or to a
      pcie-switch-upstream-port. In order for the bus to be of any use in
      the guest, it must have either a pcie-root-port or a
      pcie-switch-upstream-port attached (and one or more
      pcie-switch-downstream-ports attached to the
      pcie-switch-upstream-port).
      bc07251f
    • L
      conf: new pci controller model pci-expander-bus · 52f3d0a4
      Laine Stump 提交于
      This is a standard PCI root bus (not a bridge) that can be added to a
      440fx-based domain. Although it uses a PCI slot, this is *not* how it
      is connected into the PCI bus hierarchy, but is only used for
      control. Each pci-expander-bus provides 32 slots (0-31) that can
      accept hotplug of standard PCI devices.
      
      The usefulness of pci-expander-bus relative to a pci-bridge is that
      the NUMA node of the bus can be specified with the <node> subelement
      of <target>. This gives guest-side visibility to the NUMA node of
      attached devices (presuming that management apps only assign a device
      to a bus that has a NUMA node number matching the node number of the
      device on the host).
      
      Each pci-expander-bus also has a "busNr" attribute. The expander-bus
      itself will take the busNr specified, and all buses that are connected
      to this bus (including the pci-bridge that is automatically added to
      any expander bus of model "pxb" (see the next commit)) will use
      busNr+1, busNr+2, etc, and the pci-root (or the expander-bus with next
      lower busNr) will use bus numbers lower than busNr.
      52f3d0a4
    • C
      docs: formatdomain: document versions for video acceleration · ea9c3da4
      Cole Robinson 提交于
      clarify what version initial support was added, and when libvirt
      started supporting it for the qemu driver
      
      https://bugzilla.redhat.com/show_bug.cgi?id=657931
      ea9c3da4
    • C
      docs: domain: document blkiotune {read, write}_{bytes, iops}_sec · fd52de12
      Cole Robinson 提交于
      Added with commit 3b431929 in v1.2.2 but never documented
      
      https://bugzilla.redhat.com/show_bug.cgi?id=1313613
      fd52de12
  20. 08 4月, 2016 2 次提交
  21. 05 4月, 2016 1 次提交
  22. 30 3月, 2016 1 次提交
  23. 29 3月, 2016 1 次提交