Add device nodes for the R8A7790 internal PCI bridge devices.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: NIan Molton <ian.molton@codethink.co.uk>
[Sergei: added several properties to the PCI bridge nodes]
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch support PIO transfer only at this point
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds a default PCIe bus clock node.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
[horms+renesas@verge.net.au: resolved conflict]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds the device tree clock node for the PCIe Controller
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
[horms+renesas@verge.net.au: resolved conflict]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds a default PCIe bus clock node.
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds the device tree clock node for the PCIe Controller
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

audio_clk_a/b/c are required from sound driver
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This patch support PIO transfer only at this point
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Define the Henninger board dependent part of the I2C2 device node.

Based on the Koelsch I2C2 device tree patch by Wolfram Sang.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

A second i2c6 node was a added by
05e234a187058ee ("ARM: shmobile: koelsch dts: Add VDD MPU regulator for
DVFS"). Merge this into the existing node.

Also shuffle i2c nodes so they are all together.

Cc: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Due to an error when merging df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") a duplicate i2c3 node.

This patch moves the duplicate and moves to old node to
be closer to the other new i2c nodes.

Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Update the Lager DTS to make use of the new unified legacy
memory map where the legacy window on Lager and Koelsch
have the same size.

With this change in place the code gets aligned with the
documentation.

After update the Lager board has the following map:
Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff)
Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff)

Before the update the old map looked like this:
Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff)
Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff)

Tested with and without LPAE on r8a7790 Lager.
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile:
lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong
node.

This patch moves them to their correct location in the pfc node.

Cc: Ben Dooks <ben.dooks@codethink.co.uk>
Reported-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board
to ensure these are setup correctly at initialisation time. The i2c0
and i2c3 busses are connected to single function pins.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to patch title]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as
these busses all have devices on them that can be probed even if they
are no drivers yet.
Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk>
[horms+renesas@verge.net.au: Added shmobile to title]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.

- voltage-tolerance = 1%
  It reflects the tolerance for the CPU voltage defined inside the OPP
  table. Due to the lack of proper OPP definition, use an arbitrary safe
  value.
- clock-latency = 300 us
  Approximate worst-case latency to do a full DVFS transition for every
  OPPs. Due to the lack of HW information, use an arbitrary safe value.
  Note: The term transition-latency will be more accurate to define this
  value since the clock transition latency is not the only parameter that
  will define the overall DVFS transition.
- operating-points = < kHz - uV >
  List of 6 operating points. All of them are using the same voltage
  since DVS is not supported in R-CAR Gen2.
- clocks
  phandle to the CPU clock source. This clock source is used for all the
  2 CortexA15 located inside the same cluster.
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c6 node, to allow the generic CPUFreq driver to use it.

Enable the i2c6 pin mux and the device node as well since the
da9210 is connected to that bus.

Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add needed information inside CPU0 for the generic cpufreq-cpu0 driver.

- voltage-tolerance = 1%
  It reflects the tolerance for the CPU voltage defined inside the OPP
  table. Due to the lack of proper OPP definition, use an arbitrary safe
  value.
- clock-latency = 300 us
  Approximate worst-case latency to do a full DVFS transition for every
  OPPs. Due to the lack of HW information, use an arbitrary safe value.
  Note: The term transition-latency will be more accurate to define this
  value since the clock transition latency is not the only parameter that
  will define the overall DVFS transition.
- operating-points = < kHz - uV >
  List of 6 operating points. All of them are using the same voltage
  since the valid Vmin voltage is not documented in the HW spec.
- clocks
  phandle to the CPU clock source. This clock source is used for all the
  4 CortexA15 located inside the same cluster.
Signed-off-by: NBenoit Cousson <bcousson+renesas@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0]
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

The CA15 cluster is capable of voltage scaling. Add the regulator
in the i2c3 node, to allow the generic CPUFreq driver to use it.

Enable the i2c3 pin mux and the device node as well since the
da9210 is connected to that bus.

Note: In R-CAR Gen2, each frequency is using the same voltage,
and DVS control is not used. Therefore, this patch set the
voltage(Vmin/Vmax) to 1000mv.
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
[gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS]
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.

Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

As early printk support is not enabled in the kernel in the
shmobile defconfig it does not make much sense to provide for
it in the default command line.
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

And make the node name numbering match the label numbering.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: devicetree@vger.kernel.org
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle
Correction(DCC) to operate safely at frequencies >= 1.4GHz.

Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides
this support.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTero Kristo <t-kristo@ti.com>

Adds HDMI audio sDMA properties.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Adds HDMI audio sDMA properties.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Add the necessary DTS nodes to enable the micro-HDMI output on Parlor
board.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Alto35 expansion board has a ZIF connector for a 3.5'' LCD.
Add a common include file for this configuration, and use it
on Alto35.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Chestnut43, Gallop43 and Palo43 expansion boards have a ZIF connector
for a 4.3'' LCD. Add a common include file for this configuration, and
use it on relevant expansion boards.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Summit and Tobi expansion boards have a HDMI connector with a TFP410
encoder. Add a common include file for this configuration, and then
use it for Summit and Tobi.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

Looks like quite a few omap3 boards have sharp ls037v7dw01 that's
configured as various panel dpi entries for whatever legacy reasons.
For device tree based support, let's just configure these properly for
panel ls037v7dw01 instead of panel dpi.

This patch creates a common file for panel ls037v7dw01, and makes
boards ldp and omap3-evm to use it.

The ls037v7dw01 also seems to be coupled with an ad7846 touchscreen
controller for the omaps, so let's add a basic configuration for
the touchscreen also using the default values.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

This patch add support for lcd display on gta04 board. Display control
is connected to spi (used spi bitbang driver).
Signed-off-by: NMarek Belisko <marek@goldelico.com>
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>

omap5-uevm has a single HDMI output. Add the necessary display
information, including pinmuxing.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>