- 26 6月, 2014 1 次提交
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由 Ben Dooks 提交于
Add device nodes for the R8A7790 internal PCI bridge devices. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Reviewed-by: NIan Molton <ian.molton@codethink.co.uk> [Sergei: added several properties to the PCI bridge nodes] Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Tested-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 17 6月, 2014 27 次提交
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由 Kuninori Morimoto 提交于
This patch support PIO transfer only at this point Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
This patch adds a default PCIe bus clock node. Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> [horms+renesas@verge.net.au: resolved conflict] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
This patch adds the device tree clock node for the PCIe Controller Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> [horms+renesas@verge.net.au: resolved conflict] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
This patch adds a default PCIe bus clock node. Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Phil Edworthy 提交于
This patch adds the device tree clock node for the PCIe Controller Signed-off-by: NPhil Edworthy <phil.edworthy@renesas.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
audio_clk_a/b/c are required from sound driver Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
This patch support PIO transfer only at this point Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Sergei Shtylyov 提交于
Define the Henninger board dependent part of the I2C2 device node. Based on the Koelsch I2C2 device tree patch by Wolfram Sang. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
A second i2c6 node was a added by 05e234a187058ee ("ARM: shmobile: koelsch dts: Add VDD MPU regulator for DVFS"). Merge this into the existing node. Also shuffle i2c nodes so they are all together. Cc: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
Due to an error when merging df40f256b18300e1 ("ARM: shmobile: lager: add i2c1, i2c2 pins") a duplicate i2c3 node. This patch moves the duplicate and moves to old node to be closer to the other new i2c nodes. Cc: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Update the Lager DTS to make use of the new unified legacy memory map where the legacy window on Lager and Koelsch have the same size. With this change in place the code gets aligned with the documentation. After update the Lager board has the following map: Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff) Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff) Before the update the old map looked like this: Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff) Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff) Tested with and without LPAE on r8a7790 Lager. Signed-off-by: NMagnus Damm <damm+renesas@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile: lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong node. This patch moves them to their correct location in the pfc node. Cc: Ben Dooks <ben.dooks@codethink.co.uk> Reported-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Ben Dooks 提交于
Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board to ensure these are setup correctly at initialisation time. The i2c0 and i2c3 busses are connected to single function pins. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> [horms+renesas@verge.net.au: Added shmobile to patch title] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Ben Dooks 提交于
Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as these busses all have devices on them that can be probed even if they are no drivers yet. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> [horms+renesas@verge.net.au: Added shmobile to title] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Gaku Inami 提交于
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in R-CAR Gen2. - clocks phandle to the CPU clock source. This clock source is used for all the 2 CortexA15 located inside the same cluster. Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Gaku Inami 提交于
The CA15 cluster is capable of voltage scaling. Add the regulator in the i2c6 node, to allow the generic CPUFreq driver to use it. Enable the i2c6 pin mux and the device node as well since the da9210 is connected to that bus. Note: In R-CAR Gen2, each frequency is using the same voltage, and DVS control is not used. Therefore, this patch set the voltage(Vmin/Vmax) to 1000mv. Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Benoit Cousson 提交于
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since the valid Vmin voltage is not documented in the HW spec. - clocks phandle to the CPU clock source. This clock source is used for all the 4 CortexA15 located inside the same cluster. Signed-off-by: NBenoit Cousson <bcousson+renesas@baylibre.com> [gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0] Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Benoit Cousson 提交于
The CA15 cluster is capable of voltage scaling. Add the regulator in the i2c3 node, to allow the generic CPUFreq driver to use it. Enable the i2c3 pin mux and the device node as well since the da9210 is connected to that bus. Note: In R-CAR Gen2, each frequency is using the same voltage, and DVS control is not used. Therefore, this patch set the voltage(Vmin/Vmax) to 1000mv. Signed-off-by: NBenoit Cousson <bcousson@baylibre.com> [gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS] Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Geert Uytterhoeven 提交于
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks. Cfr. the r8a7790 version by Ben Dooks. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Yoshihiro Shimoda 提交于
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Yoshihiro Shimoda 提交于
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 16 6月, 2014 2 次提交
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由 Simon Horman 提交于
As early printk support is not enabled in the kernel in the shmobile defconfig it does not make much sense to provide for it in the default command line. Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Geert Uytterhoeven 提交于
And make the node name numbering match the label numbering. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 08 6月, 2014 2 次提交
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由 Mark Charlebois 提交于
Patch to prevent warning of a buggy compiler when using clang and the ARM_UNWIND option. Clang defines (at least on the current trunk) GNUC, GNUC_MINOR, and GNUC_PATCHLEVEL to 4, 2, and 1 respectively. This version of GCC gets flagged as buggy, but it isn't actually an issue with clang so the patch will do what it did before unless clang is defined and then it will not report the GCC version as an issue. Signed-off-by: NMark Charlebois <charlebm@gmail.com> Signed-off-by: NBehan Webster <behanw@converseincode.com>
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由 Behan Webster 提交于
With compilers which follow the C99 standard (like modern versions of gcc and clang), "extern inline" does the wrong thing (emits code for an externally linkable version of the inline function). "static inline" is the correct choice instead. Author: Behan Webster <behanw@converseincode.com> Signed-off-by: NBehan Webster <behanw@converseincode.com> Reviewed-by: NMark Charlebois <charlebm@gmail.com>
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- 07 6月, 2014 5 次提交
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由 Joe Perches 提交于
This typedef is unnecessary and should just be removed. Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Boris BREZILLON 提交于
sam9x5 SoCs have the following errata: "RTC: Interrupt Mask Register cannot be used Interrupt Mask Register read always returns 0." Hence we should not rely on what IMR claims about already masked IRQs and just disable all IRQs. Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: NBryan Evenson <bevenson@melinkcorp.com> Reviewed-by: NJohan Hovold <johan@hovold.com> Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com> Cc: Bryan Evenson <bevenson@melinkcorp.com> Cc: Andrew Victor <linux@maxim.org.za> Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Mark Roszko <mark.roszko@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Nishanth Menon 提交于
OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle Correction(DCC) to operate safely at frequencies >= 1.4GHz. Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides this support. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Andrii Tseglytskyi 提交于
Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x. MPU DPLL has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). For further information, See the note on OMAP5432 Technical Reference Manual(SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5" chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by: NAndrii Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: NTaras Kondratiuk <taras@ti.com> Signed-off-by: NJ Keerthy <j-keerthy@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> [t-kristo@ti.com: added TRM / DM references for DCC clock rate] Signed-off-by: NTero Kristo <t-kristo@ti.com>
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由 Linus Torvalds 提交于
Russell King points out that my ARM merge (commit eb3d3ec5) was broken wrt the arch/arm/mach-mvebu/board-v7.c file, leaving in a stale l2x0_of_init() call (it's now handled by the DT description). Which is kind of embarrassing, since I knew about it as it wasn't the only file that had similar merge issues. At least I got the other ones right. Reported-by: NRussell King <rmk@arm.linux.org.uk> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 06 6月, 2014 1 次提交
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由 Santosh Shilimkar 提交于
Laura's series removed the meminfo structure and its no longer available. Update keystone code to remove the usage of it. Reported-by: NRussell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 05 6月, 2014 2 次提交
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由 Vince Weaver 提交于
Make the ARM perf code use the new common PMU interrupt disabled code. This allows perf to work on ARM machines without a working PMU interrupt (for example, raspberry pi). Acked-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NVince Weaver <vincent.weaver@maine.edu> [peterz: applied changes suggested by Will] Signed-off-by: NPeter Zijlstra <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1405161712190.11099@vincent-weaver-1.umelst.maine.edu [ Small readability tweaks to the code. ] Signed-off-by: NIngo Molnar <mingo@kernel.org> Signed-off-by: NIngo Molnar <mingo@kernel.org>
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由 Nicolas Pitre 提交于
It is better not to think about compute capacity as being equivalent to "CPU power". The upcoming "power aware" scheduler work may create confusion with the notion of energy consumption if "power" is used too liberally. This contains the architecture visible changes. Incidentally, only ARM takes advantage of the available pow^H^H^Hcapacity scaling hooks and therefore those changes outside kernel/sched/ are confined to one ARM specific file. The default arch_scale_smt_power() hook is not overridden by anyone. Replacements are as follows: arch_scale_freq_power --> arch_scale_freq_capacity arch_scale_smt_power --> arch_scale_smt_capacity SCHED_POWER_SCALE --> SCHED_CAPACITY_SCALE SCHED_POWER_SHIFT --> SCHED_CAPACITY_SHIFT The local usage of "power" in arch/arm/kernel/topology.c is also changed to "capacity" as appropriate. Signed-off-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NPeter Zijlstra <peterz@infradead.org> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Morten Rasmussen <morten.rasmussen@arm.com> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: linaro-kernel@lists.linaro.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mark Brown <broonie@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Cc: Vincent Guittot <vincent.guittot@linaro.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Link: http://lkml.kernel.org/n/tip-48zba9qbznvglwelgq2cfygh@git.kernel.orgSigned-off-by: NIngo Molnar <mingo@kernel.org>
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