1. 04 7月, 2022 3 次提交
    • A
      mlxsw: Configure ingress RIF classification · fea20547
      Amit Cohen 提交于
      Before layer 2 forwarding, the device classifies an incoming packet to
      a FID. The classification is done based on one of the following keys:
      
      1. FID
      2. VNI (after decapsulation)
      3. VID / {Port, VID}
      
      After classification, the FID is known, but also all the attributes of
      the FID, such as the router interface (RIF) via which a packet that
      needs to be routed will ingress the router block.
      
      In the legacy model, when a RIF was created / destroyed, it was
      firmware's responsibility to update it in the previously mentioned FID
      classification records. In the unified bridge model, this responsibility
      moved to software.
      
      The third classification requires to iterate over the FID's {Port, VID}
      list and issue SVFA write with the correct mapping table according to the
      port's mode (virtual or not). We never map multiple VLANs to the same FID
      using VID->FID mapping, so such a mapping needs to be performed once.
      
      When a new FID classification entry is configured and the FID already has
      a RIF, set the RIF as part of SVFA configuration.
      
      The reverse needs to be done when clearing a RIF from a FID. Currently,
      clearing is done by issuing mlxsw_sp_fid_rif_set() with a NULL RIF pointer.
      Instead, introduce mlxsw_sp_fid_rif_unset().
      
      Note that mlxsw_sp_fid_rif_set() is called after the RIF is fully
      operational, so it conforms to the internal requirement regarding
      SVFA.irif_v: "Must not be set for a non-enabled RIF".
      
      Do not set the ingress RIF for rFIDs, as the {Port, VID}->rFID entry is
      configured by firmware when legacy model is used, a next patch will
      handle this configuration for rFIDs and unified bridge model.
      Signed-off-by: NAmit Cohen <amcohen@nvidia.com>
      Reviewed-by: NPetr Machata <petrm@nvidia.com>
      Signed-off-by: NIdo Schimmel <idosch@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fea20547
    • A
      mlxsw: spectrum_fid: Configure VNI to FID classification · 8cfc7f77
      Amit Cohen 提交于
      In the new model, SFMR no longer configures both VNI->FID and FID->VNI
      classifications, but only the later. The former needs to be configured via
      SVFA.
      
      Add SVFA configuration as part of vni_set() and vni_clear().
      Signed-off-by: NAmit Cohen <amcohen@nvidia.com>
      Reviewed-by: NPetr Machata <petrm@nvidia.com>
      Signed-off-by: NIdo Schimmel <idosch@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8cfc7f77
    • A
      mlxsw: Configure egress VID for unicast FDB entries · 53d7ae53
      Amit Cohen 提交于
      Using unified bridge model, firmware no longer configures the egress VID
      "under the hood" and moves this responsibility to software.
      
      For layer 2, this means that software needs to determine the egress VID
      for both unicast (i.e., FDB) and multicast (i.e., MDB and flooding) flows.
      
      Unicast FDB records and unicast LAG FDB records have new fields - "set_vid"
      and "vid", set them. For records which point to router port, do not set
      these fields.
      Signed-off-by: NAmit Cohen <amcohen@nvidia.com>
      Reviewed-by: NPetr Machata <petrm@nvidia.com>
      Signed-off-by: NIdo Schimmel <idosch@nvidia.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      53d7ae53
  2. 03 7月, 2022 31 次提交
  3. 02 7月, 2022 6 次提交
    • D
      Merge branch 'lan937x-dsa-driver' · 8e60a041
      David S. Miller 提交于
      Arun Ramadoss says:
      
      ====================
      net: dsa: microchip: DSA Driver support for LAN937x
      
      LAN937x is a Multi-Port 100BASE-T1 Ethernet Physical Layer switch
      compliant with the IEEE 802.3bw-2015 specification. The device provides
      100 Mbit/s transmit and receive capability over a single Unshielded
      Twisted Pair (UTP) cable. LAN937x is successive revision of KSZ series
      switch.
      This series of patches provide the DSA driver support for
      Microchip LAN937X switch through MII/RMII interface. The RGMII interface
      support will be added in the follow up series.  LAN937x uses the most of
      functionality of KSZ9477.
      
      The LAN937x switch series family consists of following SKUs:
      
      LAN9370:
        - 4 T1 Phys
        - 1 RGMII port
      
      LAN9371:
        - 3 T1 Phys & 1 TX Phy
        - 2 RGMII ports
      
      LAN9372:
        - 5 T1 Phys & 1 TX Phy
        - 2 RGMII ports
      
      LAN9373:
        - 5 T1 Phys
        - 2 RGMII
        - 1 SGMII port
      
      LAN9374:
        - 6 T1 Phys
        - 2 RGMII ports
      
      Changes in v15:
      - fixed compilation issue.
      - Updated the phylink_mac_link_up to check only for 10/100/1000 speed.
      
      Changes in v14:
      - Updated the patch series to latest ksz code refactoring.
      - RGMII register configuration is removed from the series. It will be added in
      the follow up patch series.
      
      Changes in v13:
      - Fixed the compilation issue in patch 5 and 6
      
      Changes in v12:
      - Removed the reduntant spi indirect enable in lan937x_init
      - Used the ksz_port_stp_state_set function
      - Apply rgmii internal delay only if it is rgmii port
      - Set the bit for 100baseTx in phylink_get_caps
      - Moved the ethtool related API from patch 5 to 7
      - Moved lan_alu_entry struct in lan937x_dev.h from patch 5 to 9
      - Moved lan_vlan_entry in lan937x_dev.h from patch 5 to 10
      - Used the ksz_get_stats64 function for get_stats64 hook
      - Splitted the patch 5. one for port configuration, spi driver, phy read &
        write and mtu configuration.
      - Updated the indentation in ethernet-controller.yaml
      - lan937x.yaml: Removed the blank lines, updated the ethernet handle to macb0.
        Added the rgmii internal delay only for the ports.
      
      Changes in v11:
      - Tagged as RFC to get the feedback for the subpatches 1/10, 5/10 and 6/10
      
      Changes in v10:
      - dsa.yaml: dropped moving mdio properties to dsa.yaml as per the feedback
      https://patchwork.kernel.org/project/netdevbpf/patch/20220318085540.281721-3-prasanna.vengateshan@microchip.com/#24787466
      - microchip,lan937x.yaml: Naming convention changes in the example
      - lan937x_main.c: Moving configurations from lan937x_reset_switch() to setup()
      - lan937x_main.c: helper function has been introduced for
        lan937x_internal_phy_read & write
      - lan937x_dev.h: lan_alu_struct struct data type changes
      - lan937x_main.c: lan937x_get_stats64 make non blocking
      - lan937x_main.c: modified lan937x_port_mirror_add to include extack
      
      Changes in v9:
      - lan937x_main.c: of_node_put() correction in lan937x_parse_dt_rgmii_delay
      - lan937x_dev.c: removed the interface checks from lan937x_apply_rgmii_delay.
      - changes in ethernet-controller.yaml and dsa.yaml
      
      Changes in v8:
      - lan937x_dev.c: fixed lan937x_r_mib_pkt warning in the sub patches
      - lan937x_main.c: phylink_autoneg_inband() check removed in
        lan937x_phylink_mac_link_up()
      - lan937x_main.c: made legacy_pre_march2020 = false as this is non-legacy driver
        and indentation correction in lan937x_phylink_mac_link_up()
      - removed unnecessary parenthesis in lan937x_get_strings()
      
      Changes in v7:
      - microchip,lan937x.yaml: *-internal-delay-ps enum values & commit messages
        corrections
      - lan937x_main.c: removed phylink_validate() and added phylink_get_caps()
      - lan937x_main.c: added support for ethtool standard stats   (get_eth_*_stats
        and get_stats64)
      - lan937x_main.c: removed unnecessary PVID read from lan937x_port_vlan_del()
      - integrated the changes of ksz9477 multi bridging support to lan937x dev and
        tested both multi bridging and STP
      - lan937x_port_vlan_del - dummy pvid read removed
      
      Changes in v6:
      - microchip_t1.c: There was new merge done in the net-next tree for
        microchip_1.c after the v5 submission. Hence rebased it for v6.
      
      Changes in v5:
      - microchip,lan937x.yaml: Added mdio properties detail
      - microchip,lan937x.yaml: *-internal-delay-ps added under port node
      - lan937x_dev.c: changed devm_mdiobus_alloc from of_mdiobus_register as suggested
        by Vladimir
      - lan937x_dev.c: added dev_info for rgmii internal delay & error message to user
        in case of out of range values
      - lan937x_dev.c: return -EOPNOTSUPP for C45 regnum values for
        lan937x_sw_mdio_read & write operations
      - return from function with out storing in a variable
      - lan937x_main.c: Added vlan_enable info in vlan_filtering API
      - lan937x_main.c: lan937x_port_vlan_del: removed unintended PVID write
      
      Changes in v4:
      - tag_ksz.c: cpu_to_be16 to  put_unaligned_be16
      - correct spacing in comments
      - tag_ksz.c: NETIF_F_HW_CSUM fix is integrated
      - lan937x_dev.c: mdio_np is removed from global and handled locally
      - lan937x_dev.c: unused functions removed lan937x_cfg32 & lan937x_port_cfg32
      - lan937x_dev.c: lan937x_is_internal_100BTX_phy_port function name changes
      - lan937x_dev.c: RGMII internal delay handling for MAC. Delay values are
        retrieved from DTS and updated
      - lan937x_dev.c: corrected mutex operations for few dev variables
      - microchip,lan937x.yaml: introduced rx-internal-delay-ps &
        tx-internal-delay-ps for RGMII internal delay
      - lan937x_dev.c: Unnecessary mutex_lock has been removed
      - lan937x_main.c: PHY_INTERFACE_MODE_NA handling for lan937x_phylink_validate
      - lan937x_main.c: PORT_MIRROR_SNIFFER check in right place
      - lan937x_main.c: memset is used instead of writing 0's individually in
        lan937x_port_fdb_add function
      - lan937x_main.c: Removed \n from NL_SET_ERR_MSG_MOD calls
      
      Changes in v3:
      - Removed settings of cnt_ptr to zero and the memset()
        added a cleanup patch which moves this into ksz_init_mib_timer().
      - Used ret everywhere instead of rc
      - microchip,lan937x.yaml: Remove mdio compatible
      - microchip_t1.c: Renaming standard phy registers
      - tag_ksz.c: LAN937X_TAIL_TAG_OVERRIDE renaming
        LAN937X_TAIL_TAG_BLOCKING_OVERRIDE
      - tag_ksz.c: Changed Ingress and Egress naming convention based on
        Host
      - tag_ksz.c: converted to skb_mac_header(skb) from
        (is_link_local_ether_addr(hdr->h_dest))
      - lan937x_dev.c: Removed BCAST Storm protection settings since we
        have Tc commands for them
      - lan937x_dev.c: Flow control setting in lan937x_port_setup function
      - lan937x_dev.c: RGMII internal delay added only for cpu port,
      - lan937x_dev.c: of_get_compatible_child(node,
        "microchip,lan937x-mdio") to of_get_child_by_name(node, "mdio");
      - lan937x_dev.c:lan937x_get_interface API: returned
        PHY_INTERFACE_MODE_INTERNAL instead of PHY_INTERFACE_MODE_NA
      - lan937x_main.c: Removed compat interface implementation in
        lan937x_config_cpu_port() API & dev_info corrected as well
      - lan937x_main.c: deleted ds->configure_vlan_while_not_filtering
        = true
      - lan937x_main.c: Added explanation for lan937x_setup lines
      - lan937x_main.c: FR_MAX_SIZE correction in lan937x_get_max_mtu API
      - lan937x_main.c: removed lan937x_port_bridge_flags dummy functions
      - lan937x_spi.c - mdiobus_unregister to be added to spi_remove
        function
      - lan937x_main.c: phy link layer changes
      - lan937x_main.c: port mirroring: sniff port selection limiting to
        one port
      - lan937x_main.c: Changed to global vlan filtering
      - lan937x_main.c: vlan_table array to structure
      - lan937x_main.c -Use extack instead of reporting errors to Console
      - lan937x_main.c - Remove cpu_port addition in vlan_add api
      - lan937x_main.c - removed pvid resetting
      
      Changes in v2:
      - return check for register read/writes
      - dt compatible compatible check is added against chip id value
      - lan937x_internal_t1_tx_phy_write() is renamed to
        lan937x_internal_phy_write()
      - lan937x_is_internal_tx_phy_port is renamed to
        lan937x_is_internal_100BTX_phy_port as it is 100Base-Tx phy
      - Return value for lan937x_internal_phy_write() is -EOPNOTSUPP
        in case of failures
      - Return value for lan937x_internal_phy_read() is 0xffff
        for non existent phy
      - cpu_port checking is removed from lan937x_port_stp_state_set()
      - lan937x_phy_link_validate: 100baseT_Full to 100baseT1_Full
      - T1 Phy driver is moved to drivers/net/phy/microchip_t1.c
      - Tx phy driver support will be added later
      - Legacy switch checkings in dts file are removed.
      - tag_ksz.c: Re-used ksz9477_rcv for lan937x_rcv
      - tag_ksz.c: Xmit() & rcv() Comments are corrected w.r.to host
      - net/dsa/Kconfig: Family skew numbers altered in ascending order
      - microchip,lan937x.yaml: eth is replaced with ethernet
      - microchip,lan937x.yaml: spi1 is replaced with spi
      - microchip,lan937x.yaml: cpu labelling is removed
      - microchip,lan937x.yaml: port@x value will match the reg value now
      ====================
      8e60a041
    • A
      net: dsa: microchip: add LAN937x in the ksz spi probe · c8fac9d0
      Arun Ramadoss 提交于
      This patch add the LAN937x part support in the existing ksz_spi_probe.
      Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c8fac9d0
    • A
      net: dsa: microchip: lan937x: add phylink_mac_config support · a0cb1aa4
      Arun Ramadoss 提交于
      This patch add support for phylink_mac_config dsa hook. It configures
      the mac for MII/RMII modes. The RGMII mode will be added in the future
      patches.
      Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a0cb1aa4
    • A
      net: dsa: microchip: lan937x: add phylink_mac_link_up support · f597d3ad
      Arun Ramadoss 提交于
      This patch add support for phylink_mac_link_up. It configures the mac
      for the speed, flow control and duplex mode.
      Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f597d3ad
    • A
      net: dsa: microchip: lan937x: add phylink_get_caps support · c14e878d
      Arun Ramadoss 提交于
      The internal phy of the LAN937x are capable of 100Mbps Full duplex. The
      xMII port of switch is capable of 10Mbps Full & Half Duplex, 100Mbps
      Full & Half Duplex and 1000Mbps Half duplex. xMII port also supports Tx
      and Rx Flow control.
      Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c14e878d
    • A
      net: dsa: microchip: lan937x: add MTU and fast_age support · ab882368
      Arun Ramadoss 提交于
      This patch add the support for port_max_mtu, port_change_mtu and
      port_fast_age dsa functionality.
      Signed-off-by: NArun Ramadoss <arun.ramadoss@microchip.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ab882368