- 16 3月, 2022 3 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - Added I2C escape to support query exist - Functionality to get pipe from stream context - debugfs entry fixes - Block zstate when more than one plane enabled - Update to engine ddc - Reading lante status during LT fixes - Null point filters - [FW Promotion] Release 0.0.108.0 Acked-by: NAgustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
drm/amd/display: 3.2.176 This version brings along following fixes: - move FPU operations from dcn21 to dml/dcn20 folder - move FPU-related code from dcn20 to dml folder - Fix compile error from TO_CLK_MGR_INTERNAL - Fix double free during GPU reset on DC streams - Add NULL check - [FW Promotion] Release 0.0.107.0 - enable dcn315/316 s0i2 support - handle DP2.0 RX with UHBR20 but not UHBR13.5 support - disable HPD SW timer for passive dongle type 1 only - add gamut coefficient set A and B - merge two duplicated clock_source_create - Add link dp trace support - move FPU associated DCN303 code to DML folder - Release AUX engine after failed acquire - Add minimal pipe split transition state - Clean up fixed VS PHY test w/a function - fix the clock source contruct for dcn315 - cleaning up smu_if to add future flexibility - fix deep color ratio - add debug option to bypass ssinfo from bios for dcn315 Acked-by: NAlan Liu <HaoPing.Liu@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Sung Joon Kim 提交于
[why] Need to provide this workaround only for type 1 passive dongle [how] Detect if dongle is type 1 or 2. And use it to determine if w/a is needed. Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com> Acked-by: NAlan Liu <HaoPing.Liu@amd.com> Signed-off-by: NSung Joon Kim <sungjoon.kim@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 05 3月, 2022 2 次提交
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由 Aric Cyr 提交于
drm/amd/display: 3.2.175 This version brings along following fixes: - Remove invalid RDPCS Programming in DAL - Make functional resource functions non-static - Reset VIC if HDMI_VIC is present - Add frame alternate 3D & restrict HW packed on dongles - Reg to turn on/off PSR Power seq in FSM - Modify plane removal sequence to avoid hangs - Pass HostVM enable flag into DCN3.1 DML - DC Validation failures - Program OPP before ODM - Refactor fixed VS w/a for PHY tests - Pass deep sleep disabled allow info to dmub fw - Refine the EDID override - [FW Promotion] Release 0.0.106.0 - Add verify_link_cap back for hdmi Acked-by: NAlan Liu <HaoPing.Liu@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Robin Chen 提交于
[Why] The deep sleep mode need to be disabled in some PSR scenario. Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NAlan Liu <HaoPing.Liu@amd.com> Signed-off-by: NRobin Chen <robin.chen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 03 3月, 2022 1 次提交
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由 Shah Dharati 提交于
[Why] PSR Power on/off is done in PSR. Add a dc_debug option and dmub setting to use PHY implementation of this instead. [How] Add a dc_debug option and dmub setting to use PHY FSM Power up/down for PSR. Co-authored-by: NShah Dharati <dharati.shah@amd.com> Reviewed-by: NHansen Dsouza <hansen.dsouza@amd.com> Acked-by: NAlan Liu <HaoPing.Liu@amd.com> Signed-off-by: NShah Dharati <dharati.shah@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 24 2月, 2022 4 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - add debug option to bypass ssinfo from bios. - Refactor fixed VS logic for non-transparent mode - add cable ID support for usb c connector - clear remote dc_sink when stop mst - Ignore Transitional Invalid Link Rate Error Message - Fix wrong resolution with DP/VGA adapter - Refactor PSR DPCD caps detection - Set compbuf size to min at prep prevent overbook crb - lock/un-lock cursor if odm pipe split used Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Charlene Liu 提交于
[Why&How] add debug option to bypass ssinfo from bios. Reviewed-by: NChris Park <Chris.Park@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NCharlene Liu <Charlene.Liu@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[how] Call to DMUB to retrieve usb c cable ID data from PD firmware. If cable id is retrieved from DMUB, skip reading cable ID from RX. Reviewed-by: NGeorge Shen <George.Shen@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Po Ting Chen 提交于
[Why] To move the PSR DPCD caps detection into detect_edp_sink_caps() Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NPo Ting Chen <robin.chen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 17 2月, 2022 2 次提交
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由 Aric Cyr 提交于
This version brings along the following fixes: -Fixes bugs for dsc mst hub -Enables 29 denial itnerface by default -Fixes dmub outbox notificatoin Acked-by: NJasdeep Dhillon <jdhillon@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NJasdeep Dhillon <jdhillon@amd.com> Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 2月, 2022 1 次提交
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由 Roman Li 提交于
[Why] pflip interrupt order are mapped 1 to 1 to otg id. e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2... Linux DM registers pflip interrupts per number of crtcs. In fused pipe case crtc numbers can be less than otg id. e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2 so DM only registers irq_src 26,27. This is a bug since if pipe#2 remains unfused DM never gets otg2 pflip interrupt (irq_src=28) That may results in gfx failure due to pflip timeout. [How] Register pflip interrupts per max num of otg instead of num_crtc Signed-off-by: NRoman Li <Roman.Li@amd.com> Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 08 2月, 2022 3 次提交
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由 Aric Cyr 提交于
This version brings along the following fixes: -fix for build failure uninitalized error -Bug fix for DP2 using uncertified cable -limit unbounded request to 5k -fix DP LT sequence on EQ fail -Bug fixes for S3/S4 Acked-by: NJasdeep Dhillon <jdhillon@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Paul Hsieh 提交于
[Why] VBIOS light up eDP with 6bpc but driver use 8bpc without disable valid stream then re-enable valid stream. Some panels can't runtime change color depth. [How] Change fastboot timing validation function. Not only check LANE_COUNT, LINK_RATE...etc Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com> Acked-by: NJasdeep Dhillon <jdhillon@amd.com> Signed-off-by: NPaul Hsieh <paul.hsieh@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Roman Li 提交于
[Why] pflip interrupt order are mapped 1 to 1 to otg id. e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2... Linux DM registers pflip interrupts per number of crtcs. In fused pipe case crtc numbers can be less than otg id. e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2 so DM only registers irq_src 26,27. This is a bug since if pipe#2 remains unfused DM never gets otg2 pflip interrupt (irq_src=28) That may results in gfx failure due to pflip timeout. [How] Register pflip interrupts per max num of otg instead of num_crtc Signed-off-by: NRoman Li <Roman.Li@amd.com> Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 03 2月, 2022 1 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - DC refactor and bug fixes for DP links - Bug fixes for DP2 - Fix regressions causing display not light up - Improved debug trace - Improved DP AUX transfer - Updated watermark latencies to fix underflows in some modes Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Acked-by: NStylon Wang <stylon.wang@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 26 1月, 2022 7 次提交
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由 Eric Yang 提交于
[Why] To help triage issues and coordinate driver/bios release dependency [How] Only enable the new Z9 interface when debug option is set, otherwise treat Z10 only support case as Zstate disallowed. Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings along the following fixes: - Z9 improvements - Clocks management adjustments - Code cleanup - Improve DSC and MST code Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Shen, George 提交于
[Why/How] We need to handle cable capabilities for cables that support cable ID. The cable attributes are intersected with the verified link caps to determine appropriate max link rate. After determining cable attributes we update the DP receiver. Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NGeorge Shen <George.Shen@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[Why & How] DCN guard is not necessary for DP2.x relevant logic. Drop them. v2: squash in fix for misplaced #endif (Alex) Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Reviewed-by: NJerry Zuo <Jerry.Zuo@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jimmy Kizito 提交于
[Why] According to the USB4 specification, FEC and DSC should be disabled when a USB4 DPIA operates in TBT3 compatibility mode. [How] Upon detecting that a USB4 DPIA is connected to a device that is known to operate in TBT3 mode, disable FEC and DSC support if they have been reported by the TBT3 device. Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: NMeenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wenjing Liu 提交于
[why] dc_link_detect_helper has multiple purpose: 1. Detect link and local sink. 2. Verify link capability by performing detection link training. 3. Start mst topology discovery and if succeeded fails the current interface. This is difficult to maintain as item 2 has become more destructive to current dc state. The change is to decouple these sequences to its own functions. Eventually only item 2 is a destructive method and we will redesign this sequence with a more unified policy across different encoder types. Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: NChris Park <Chris.Park@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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[Why] During otg sync trigger, plane states are used to decide whether the otg is already synchronized or not. There are scenarions when otgs are disabled without plane state getting disabled and in such case the otg is excluded from synchronization. [How] Introduced pipe_idx_syncd in pipe_ctx that tracks each otgs master pipe. When a otg is disabled/enabled, pipe_idx_syncd is reset to itself. On sync trigger, pipe_idx_syncd is checked to decide whether a otg is already synchronized and the otg is further included or excluded from synchronization. v2: Don't drop is_blanked logic Reviewed-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NMustapha Ghaddar <mustapha.ghaddar@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Nmeenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Cc: torvalds@linux-foundation.org Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 1月, 2022 4 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - Organize FPU associated code to DML - Modify SMU_TIMEOUT macro - Organize dcn201 code - Address DS stays disabled problem under specific scenario - Fix black screen issue - Update DML to rev.99 - Address problem of eDP hot-plug feature Acked-by: NWayne Lin <wayne.lin@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings improvements in the following: - Drop unnecessary DCN guards - Improve Z9 interface Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] Need to disable Z9 on configurations that only support Z10 [How] Support new PMFW interface to disable Z9 Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jarif Aftab 提交于
[WHY] - We only ever want seamless boots on eDPs - The naming and logic did not match the context [HOW] - Removed unnecessary if statements - Renamed power_down_display_on_boot to seamless_boot_edp_requested and swapped the logic Reviewed-by: NMartin Leung <Martin.Leung@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NJarif Aftab <jaraftab@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 11 1月, 2022 1 次提交
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由 Linus Torvalds 提交于
This reverts commit a896f870. It causes odd flickering on my Radeon RX580 (PCI ID 1002:67df rev e7, subsystem ID 1da2:e353). Bisected right to this commit, and reverting it fixes things. Link: https://lore.kernel.org/all/CAHk-=wg9hDde_L3bK9tAfdJ4N=TJJ+SjO3ZDONqH5=bVoy_Mzg@mail.gmail.com/ Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Dave Airlie <airlied@gmail.com> Cc: Christian Koenig <christian.koenig@amd.com> Cc: Jun Lei <Jun.Lei@amd.com> Cc: Mustapha Ghaddar <mustapha.ghaddar@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: meenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Cc: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 30 12月, 2021 2 次提交
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由 Wenjing Liu 提交于
[why] Update all accesses to use hpo dp link encoder through link resource only. Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings along the following: - Fixes and improvements in the LTTPR code - Improve z-state - Fix null pointer check - Improve communication with s0i2 - Update multiple-display split policy - Add missing registers Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 12月, 2021 2 次提交
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由 Aric Cyr 提交于
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Martin Leung 提交于
why: Need interface to lower clocks when in dc (power save) mode. Must be able to work with p_state unsupported cases Can cause flicker when OS notifies us of dc state change how: added dal3 interface for KMD added pathway to query smu for this softmax added blank before clock change to override underflow added logic to change clk based on pstatesupport and softmax added logic in prepare/optimize_bw to conform while changing clocks Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NMartin Leung <Martin.Leung@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 08 12月, 2021 2 次提交
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由 Wenjing Liu 提交于
[why] A debug option is needed to temporarily force dp2 new link training fallback method for debugging purpose. Reviewed-by: NGeorge Shen <George.Shen@amd.com> Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: NWenjing Liu <wenjing.liu@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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[Why] Need to have dpia debug bits for configuring hpd delay. [How] Added hpd_delay_in_ms variable in dpia_debug_options. Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: NPavle Kotarac <Pavle.Kotarac@amd.com> Signed-off-by: Nmeenakshikumar somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 12月, 2021 5 次提交
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由 Jimmy Kizito 提交于
[Why] Certain USB4 docks do not seem to be able to handle disabling DSC once it has been enabled on an MST stream. This can result in blank displays. [How] As a work around, always enable DSC on docks exhibiting this issue. The flag to indicate the use of DSC for MST streams on a USB4 dock is set during detection of the dock and only cleared when the USB4 dock is disconnected. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings along the following: - FW promotion to 0.0.95 - DSC fixes for supported Docks - Fixes eDP display issue - Vendor LTTR workarounds - Fixes Tiled display audio issue Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NBhawanpreet.Lakha <Bhawanpreet.Lakha@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michael Strauss 提交于
[WHY] Allow changing DET size with debug flag for testing purposes Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NMichael Strauss <michael.strauss@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 George Shen 提交于
[Why] Certain LTTPR require special workarounds in order to comply with DP specifications. [How] Implement vendor specific sequences via DPCD writes to vendor-specific LTTPR registers. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NGeorge Shen <George.Shen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jimmy Kizito 提交于
[Why] Certain USB4 docks do not seem to be able to handle disabling DSC once it has been enabled on an MST stream. This can result in blank displays. [How] As a work around, always enable DSC on docks exhibiting this issue. The flag to indicate the use of DSC for MST streams on a USB4 dock is set during detection of the dock and only cleared when the USB4 dock is disconnected. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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