1. 26 6月, 2005 5 次提交
    • R
      [PATCH] ppc64: kexec support for ppc64 · fce0d574
      R Sharada 提交于
      This patch implements the kexec support for ppc64 platforms.
      
      A couple of notes:
      
      1)  We copy the pages in virtual mode, using the full base kernel
          and a statically allocated stack.   At kexec_prepare time we
          scan the pages and if any overlap our (0, _end[]) range we
          return -ETXTBSY.
      
          On PowerPC 64 systems running in LPAR (logical partitioning)
          mode, only a small region of memory, referred to as the RMO,
          can be accessed in real mode.  Since Linux runs with only one
          zone of memory in the memory allocator, and it can be orders of
          magnitude more memory than the RMO, looping until we allocate
          pages in the source region is not feasible.  Copying in virtual
          means we don't have to write a hash table generation and call
          hypervisor to insert translations, instead we rely on the pinned
          kernel linear mapping.  The kernel already has move to linked
          location built in, so there is no requirement to load it at 0.
      
          If we want to load something other than a kernel, then a stub
          can be written to copy a linear chunk in real mode.
      
      2)  The start entry point gets passed parameters from the kernel.
          Slaves are started at a fixed address after copying code from
          the entry point.
      
          All CPUs get passed their firmware assigned physical id in r3
          (most calling conventions use this register for the first
          argument).
      
          This is used to distinguish each CPU from all other CPUs.
          Since firmware is not around, there is no other way to obtain
          this information other than to pass it somewhere.
      
          A single CPU, referred to here as the master and the one executing
          the kexec call, branches to start with the address of start in r4.
          While this can be calculated, we have to load it through a gpr to
          branch to this point so defining the register this is contained
          in is free.  A stack of unspecified size is available at r1
          (also common calling convention).
      
          All remaining running CPUs are sent to start at absolute address
          0x60 after copying the first 0x100 bytes from start to address 0.
          This convention was chosen because it matches what the kernel
          has been doing itself.  (only gpr3 is defined).
      
          Note: This is not quite the convention of the kexec bootblock v2
          in the kernel.  A stub has been written to convert between them,
          and we may adjust the kernel in the future to allow this directly
          without any stub.
      
      3)  Destination pages can be placed anywhere, even where they
          would not be accessible in real mode.  This will allow us to
          place ram disks above the RMO if we choose.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NR Sharada <sharada@in.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      fce0d574
    • R
      [PATCH] ppc64 kexec: native hash clear · f4c82d51
      R Sharada 提交于
      Add code to clear the hash table and invalidate the tlb for native (SMP,
      non-LPAR) mode.  Supports 16M and 4k pages.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NR Sharada <sharada@in.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f4c82d51
    • I
      [PATCH] consolidate PREEMPT options into kernel/Kconfig.preempt · cc19ca86
      Ingo Molnar 提交于
      This patch consolidates the CONFIG_PREEMPT and CONFIG_PREEMPT_BKL
      preemption options into kernel/Kconfig.preempt.  This, besides reducing
      source-code, also enables more centralized tweaking of preemption related
      options.
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      cc19ca86
    • Z
      [PATCH] i386 CPU hotplug · f3705136
      Zwane Mwaikambo 提交于
      (The i386 CPU hotplug patch provides infrastructure for some work which Pavel
      is doing as well as for ACPI S3 (suspend-to-RAM) work which Li Shaohua
      <shaohua.li@intel.com> is doing)
      
      The following provides i386 architecture support for safely unregistering and
      registering processors during runtime, updated for the current -mm tree.  In
      order to avoid dumping cpu hotplug code into kernel/irq/* i dropped the
      cpu_online check in do_IRQ() by modifying fixup_irqs().  The difference being
      that on cpu offline, fixup_irqs() is called before we clear the cpu from
      cpu_online_map and a long delay in order to ensure that we never have any
      queued external interrupts on the APICs.  There are additional changes to s390
      and ppc64 to account for this change.
      
      1) Add CONFIG_HOTPLUG_CPU
      2) disable local APIC timer on dead cpus.
      3) Disable preempt around irq balancing to prevent CPUs going down.
      4) Print irq stats for all possible cpus.
      5) Debugging check for interrupts on offline cpus.
      6) Hacky fixup_irqs() to redirect irqs when cpus go off/online.
      7) play_dead() for offline cpus to spin inside.
      8) Handle offline cpus set in flush_tlb_others().
      9) Grab lock earlier in smp_call_function() to prevent CPUs going down.
      10) Implement __cpu_disable() and __cpu_die().
      11) Enable local interrupts in cpu_enable() after fixup_irqs()
      12) Don't fiddle with NMI on dead cpu, but leave intact on other cpus.
      13) Program IRQ affinity whilst cpu is still in cpu_online_map on offline.
      Signed-off-by: NZwane Mwaikambo <zwane@linuxpower.ca>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f3705136
    • M
      [PATCH] ppc64: Fix compile warnings in arch/ppc64/kernel/lparcfg.c · 856509d5
      Michael Ellerman 提交于
      Stephen's patch to remove LparData.h missed an include in lparcfg.c This
      fixes a few compile warnings.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      856509d5
  2. 24 6月, 2005 12 次提交
  3. 23 6月, 2005 11 次提交
    • D
      [PATCH] Maple powerdown patch · d7152fe1
      David Gibson 提交于
      Currently reset and powerdown are not implemented on the Maple board,
      and attempting to do so will (incorrectly return).  This implements
      the proper communication with the service processor, allowing correct
      reset and powerdown on the Maple board, by communicating with the
      service processor.  If somehow it's unable to communicate with the
      service processor it will loop forever instead.
      
      Note that powerdown on the Maple will power down the CPUs, but not the
      fans or other board components due to hardware and firmware
      limitations.
      Signed-off-by: NDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: NFrank Rowand <frowand@mvista.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d7152fe1
    • J
      [PATCH] pSeries - read irqs dynamically · dad32bbf
      John Rose 提交于
      For I/O DLPAR to work properly, the kernel needs to allow for dynamic
      assignment of the irq field of the pci_dev structure upon dynamic bus
      addition.  This patch moves the assignment of that field from
      pSeries_final_fixup() to pcibios_fixup_bus(), which enables dynamic
      assignment for the children of a newly added bus.
      
      Currently, pci_devs receive their irq numbers in one of two ways.  The
      irq line is either read at boot for all pci_devs, or read by the rpaphp
      module at slot enable time.  The latter is no longer sufficient for
      DLPAR addition of slots that don't qualify as PCI-hotplug capable.
      This solution handles the cases of boot and dynamic add.
      Signed-off-by: NJohn Rose <johnrose@austin.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      dad32bbf
    • M
      [PATCH] correct printing to operator panel · 8f586b22
      Mike Strosaker 提交于
      This patch corrects the printing of progress indicators to the op
      panel on p/iSeries ppc64 systems.  Each discrete reference code should
      begin with a form feed char to clear the op panel, and the first and
      second lines should be separated with a CR/LF sequence.  Padding with
      spaces is not necessary.
      
      Also, capitalize the hex value printed on the first line, to be
      consistent with the values printed by firmware, service processor,
      etc.
      
      It turns out that there's an ibm,form-feed property; this patch uses
      it in the pSeries-specific progress routine.  This patch also checks
      the number of rows and the specific width of each row (the second row
      on power5 systems can actually hold 80 characters).  If the displayed
      text is too wide for the physical display, it can be viewed in the ASM
      menus, or by selecting option 14 on the op panel.
      Signed-off-by: NMike Strosaker <strosake@austin.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      8f586b22
    • A
      [PATCH] ppc64: Add driver for BPA iommu · ae209cf1
      Arnd Bergmann 提交于
      Implementation of software load support for the BE iommu. This is very
      different from other iommu code on ppc64, since we only do a static mapping.
      The mapping is currently hardcoded but should really be read from the
      firmware, but they don't set up the device nodes yet. There is a single
      512MB DMA window for PCI, USB and ethernet at 0x20000000 for our RAM.
      
      The Cell processor can put the I/O page table either in memory like
      the hashed page table (hardware load) or have the operating system
      write the entries into memory mapped CPU registers (software load).
      
      I use the software load mechanism because I know that all I/O page
      table entries for the amount of installed physical memory fit into
      the IO TLB cache. At the point when we get machines with more than
      4GB of installed memory, we can either use hardware I/O page table
      access like the other platforms do or dynamically update the I/O
      TLB entries when a page fault occurs in the I/O subsystem.
      
      The software load can then use the macros that I have implemented
      for the static mapping in order to do the TLB cache updates.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      ae209cf1
    • A
      [PATCH] ppc64: Add driver for BPA interrupt controllers · cebf589c
      Arnd Bergmann 提交于
      Add support for the integrated interrupt controller on BPA
      CPUs. There is one of those for each SMT thread.
      
      The mapping of interrupt numbers to HW interrupt sources
      is described in arch/ppc64/kernel/bpa_iic.h.
      
      This version hardcodes the 'Spider' chip as the secondary
      interrupt controller. That is not really generic for the
      architecture, but at the moment it is the only secondary
      PIC that exists.
      
      A little more work will be needed on this as soon as
      we have boards with multiple external interrupt controllers.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cebf589c
    • A
      [PATCH] ppc64: add BPA platform type · fef1c772
      Arnd Bergmann 提交于
      This adds the basic support for running on BPA machines.
      So far, this is only the IBM workstation, and it will
      not run on others without a little more generalization.
      
      It should be possible to configure a kernel for any
      combination of CONFIG_PPC_BPA with any of the other
      multiplatform targets.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      fef1c772
    • U
      [PATCH] ppc64: add a minimal nvram driver · 5f5b4e66
      Utz Bacher 提交于
      The firmware provides the location and size of the nvram
      in the device tree, so it does not really contain any
      hardware specific bits and could be used on other
      machines as well.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      5f5b4e66
    • A
      [PATCH] ppc64: pSeries_progress -> rtas_progress · 6566c6f1
      Arnd Bergmann 提交于
      The pSeries_progress function is called from some places in the rtas code,
      which may also be used by non-pSeries platforms.
      Though pSeries is currently the only platform type that implements
      display-character, the code is actually generic enough to be part of
      the rtas subsystem.
      
      I hit a bug here because the generic rtas code tried calling ppc_md.progress,
      which points to an __init function on most platforms.
      
      We could also clear the ppc_md.progress pointer when freeing the init memory
      to make it more explicit that ppc_md.progress must not be called after
      bootup.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      6566c6f1
    • A
      [PATCH] ppc64: Split out generic rtas code from pSeries_pci.c. · c5a3c2e5
      Arnd Bergmann 提交于
      BPA is using rtas for PCI but should not be confused by
      pSeries code. This also avoids some #ifdefs. Other
      platforms that want to use rtas_pci.c could create
      their own platform_pci.c with platform specific fixups.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      c5a3c2e5
    • A
      [PATCH] ppc64: rename pSeries rtc functions into rtas_* · 773bf9c4
      Arnd Bergmann 提交于
      The rtc rtas functions are not pSeries specific but can
      also be used by BPA and other SLOF based platforms
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      773bf9c4
    • A
      [PATCH] ppc64: consolidate calibrate_decr implementations · 10f7e7c1
      Arnd Bergmann 提交于
      pSeries and maple have almost the same code for calibrate_decr,
      and BPA would need yet another copy. Instead, I'm moving the
      code to arch/ppc64/kernel/time.c.
      
      Some of the related declarations were missing from header
      files, so I'm moving those as well.
      
      It makes sense to merge this with the pmac function of the
      same name, so we end up having just one implemetation for
      iSeries and one for Open Firmware based machines.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      10f7e7c1
  4. 22 6月, 2005 12 次提交