Adding an include guard frees the preprocessor from reparsing over 2600
#defines in the cases where pci_ids.h is somehow included more than once.
This gives a tiny-but-measurable performance improvement when compiling
such files.
Signed-off-by: NRasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

These IDs are no longer referenced since kernel 3.1 so I suppose we can
remove them from pci_ids.h.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com>
Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>

Extend ECC decoding support for F16h M30h. Tested on F16h M30h with ECC
turned on using mce_amd_inj module and the patch works fine.
Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Link: http://lkml.kernel.org/r/1392913726-16961-1-git-send-email-Aravind.Gopalakrishnan@amd.comTested-by: NArindam Nath <Arindam.Nath@amd.com>
Acked-by: NH. Peter Anvin <hpa@zytor.com>
Signed-off-by: NBorislav Petkov <bp@suse.de>

This patch adds the PCI ids for the Intel SandyBridge,
IvyBridge, Haswell Client memory controller (IMC).

Cc: mingo@elte.hu
Cc: acme@redhat.com
Cc: ak@linux.intel.com
Cc: zheng.z.yan@intel.com
Cc: peterz@infradead.org
Signed-off-by: NStephane Eranian <eranian@google.com>
Signed-off-by: NPeter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1392132015-14521-4-git-send-email-eranian@google.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This patch adds the PCI ID's for HP Smart Array Gen9 controllers. Please
consider this patch for inclusion.
Signed-off-by: NMike Miller <mike.miller@hp.com>
Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>

Add PCI device IDs for AMD F15h, model 30h. They will be used in
amd_nb.c and amd64_edac.c
Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
Signed-off-by: NBorislav Petkov <bp@suse.de>

These two defines are no longer used.  They were only used by the PCI
serial driver "8250_pci" to support the original ADDI-DATA APCI-7800
card.  In that driver, PCI_VENDOR_ID_ADDIDATA_OLD has been replaced with
PCI_VENDOR_ID_AMCC which has the same value (0x10e8), and
PCI_DEVICE_ID_ADDIDATA_APCI7800 has been replaced with a local #define
PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 with the same value (0x818e).
Signed-off-by: NIan Abbott <abbotti@mev.co.uk>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

PCI_VENDOR_ID_AMCC is defined locally in
"drivers/staging/comedi/comedidev.h" for a few comedi hardware drivers,
namely "adl_pci9118", "addi_apci_1500" and "addi_apci_3120" (also
"addi_apci_1710" but that is not currently built and will probably be
removed soon).  Move the define into "include/linux/pci_ids.h" as it is
shared by several drivers (albeit all comedi drivers currently).

PCI_VENDOR_ID_AMCC happens to have the same value (0x10e8) as
PCI_VENDOR_ID_ADDIDATA_OLD.  The vendor ID is actually assigned to
Applied Micro Circuits Corporation and Addi-Data were using device IDs
assigned by AMCC on some of their earlier PCI boards. The
PCI_VENDOR_ID_ADDIDATA_OLD define is still being used by the "8250_pci"
PCI serial board driver.
Signed-off-by: NIan Abbott <abbotti@mev.co.uk>
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add CircuitCo's newly created VENDOR ID and their first board subsystem
ID for the MinnowBoard.

[bhelgaas: sort, change DEVICE_ID to SUBSYSTEM_ID]
Signed-off-by: NDarren Hart <dvhart@linux.intel.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

To put all AMD Hudson-2 device IDs together for better maintenance.

[bhelgaas: also sort Hudson-2 devices by ID]
Signed-off-by: NShane Huang <shane.huang@amd.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NTejun Heo <tj@kernel.org>
Acked-by: NJean Delvare <khali@linux-fr.org>

[jejb: move PCI_DEVICE_ID definitions to include/pci_ids.h]
Signed-off-by: NBhanu Prakash Gollapudi <bprakash@broadcom.com>
Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>

Add code to handle DRAM ECC errors decoding for Fam16h.

Tested on Fam16h with ECC turned on using the mce_amd_inj facility and
works fine.
Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
[ Boris: cleanups and clarifications ]
Signed-off-by: NBorislav Petkov <bp@suse.de>

Define PCI_VENDOR_ID_MARVELL_EXT macro for 0x1b4b vendor ID
Signed-off-by: NXiangliang Yu <yuxiangl@marvell.com>
Signed-off-by: NMyron Stowe <myron.stowe@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

Probe and store the device handle for the device 19 function 0 during
driver initialization. The device is used during fault injection.
Signed-off-by: NNiklas Söderlund <niklas.soderlund@ericsson.com>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>

The BCM4785 or sometimes named BMC4705 is a Broadcom SoC which a
Gigabit 5750 Ethernet core. The core is connected via PCI with the rest
of the SoC, but it uses some extension.

This core does not use a firmware or an eeprom.

Some devices only have a switch which supports 100MBit/s, this
currently does not work with this driver.

This patch was original written by Michael Buesch <m@bues.ch> and is in
OpenWrt for some years now.

This was tested on a Linksys WRT610N V1 and older versions of this patch
were tested by other people on different devices.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Acked-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

There are a number of pci vendor ids that are used in multiple
drivers in the comedi subsystem. Move these ids to pci_ids.h.

This also fixes some build warnings reported by the kbuild test
robot about PCI_VENDOR_ID_AMPLICON being undeclared.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Jonathan Woithe posted an out of tree enabler/control module for these
cards.  Lift the relevant identifiers and put them in the 8250_pci driver
along with code used to control custom registers on these cards.
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NJonathan Woithe <jwoithe@just42.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Otherwise it fails like this on cards like the Transcend 16GB SDHC card:

    mmc0: new SDHC card at address b368
    mmcblk0: mmc0:b368 SDC   15.0 GiB
    mmcblk0: error -110 sending status command, retrying
    mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb0

Tested on my Lenovo x200 laptop.

[bhelgaas: changelog]
Signed-off-by: NAndy Lutomirski <luto@amacapital.net>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NChris Ball <cjb@laptop.org>
CC: Manoj Iyer <manoj.iyer@canonical.com>
CC: stable@vger.kernel.org

Add support for Commtech's Fastcom Async-335 and Fastcom Async-PCIe cards
Signed-off-by: NMatt Schulte <matts@commtech-fastcom.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add support for new devices: Exar's XR17V35x family of multi-port PCIe UARTs.
Signed-off-by: NMatt Schulte <matts@commtech-fastcom.com>
Acked-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The SMBus controller in the VIA VX900 appears to be compatible with
the VIA VX855, so just add the device ID.

This closes kernel bug #43096.
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Apparently the same card model has two IDs, so this patch
complements the commit 39aced68
adding the missing one.
Signed-off-by: NFlavio Leitner <fbl@redhat.com>
Cc: stable <stable@vger.kernel.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>

Commit c3def943 have added support for
new pci ids of the 57840 board, while failing to change the obsolete value
in 'pci_ids.h'.
This patch does so, allowing the probe of such devices.
Signed-off-by: NYuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: NEilon Greenstein <eilong@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The uncore subsystem in Sandy Bridge-EP consists of 8 components:

 Ubox, Cacheing Agent, Home Agent, Memory controller, Power Control,
 QPI Link Layer, R2PCIe, R3QPI.
Signed-off-by: NZheng Yan <zheng.z.yan@intel.com>
Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1339741902-8449-9-git-send-email-zheng.z.yan@intel.comSigned-off-by: NIngo Molnar <mingo@kernel.org>

Add the F3 PCI id of F15h, model 0x10 to pci_ids.h and to the amd_nb
code which generates the list of northbridges on an AMD box. Shorten
define name while at it so that it fits into pci_ids.h.
Acked-by: NClemens Ladisch <clemens@ladisch.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: NAndreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This patch adds the Integrated Legacy Block DeviceID for the Centerton CPU.  It will be used in the GPIO and Multifunction Devices driver.
Signed-off-by: NSeth Heasley <seth.heasley@intel.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

This patch recodes the MRRS cap for 5719 A0 devices as a PCI quirk.
Signed-off-by: NMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The chip is an I/O hub used by some Atom boards.  Most of those
symbols are used in arch/x86/platform/sta2x11/sta2x11.c (to be
introduced) and in the specific drivers as well.
Signed-off-by: NAlessandro Rubini <rubini@gnudd.com>
Acked-by: NGiancarlo Asnaghi <giancarlo.asnaghi@st.com>
Cc: Alan Cox <alan@linux.intel.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

I've received complaints that the numa_node attribute for family
15h model 00-0fh (e.g. Interlagos) northbridge functions shows
-1 instead of the proper node ID.

Correct this with attached quirks (similar to quirks for other
AMD CPU families used in multi-socket systems).
Signed-off-by: NAndreas Herrmann <andreas.herrmann3@amd.com>
Cc: Frank Arnold <frank.arnold@amd.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
Link: http://lkml.kernel.org/r/20111202072143.GA31916@alberich.amd.comSigned-off-by: NIngo Molnar <mingo@elte.hu>

Signed-off-by: NKeng-Yu Lin <kengyu@canonical.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>

In the OCZ RevoDrive3/zDrive R4 series, the "OCZ SuperScale Storage
Controller" with "Virtualized Controller Architecture 2.0" really seems
to be a Marvell 88SE9485 part, with OCZ firmware/BIOS.

Developed and tested on OCZ RevoDrive3 120GB [PCI 1b85:1021]

Should work on:
- OCZ RevoDrive3 (2x SandForce 2281)
- OCZ RevoDrive3 X2 (4x SandForce 2281)
- OCZ zDrive R4 CM84 (4x SandForce 2281)
- OCZ zDrive R4 CM88 (8x SandForce 2281)
- OCZ zDrive R4 RM84 (4x SandForce 2582)
- OCZ zDrive R4 RM88 (8x SandForce 2582)

All of this because a friend recently bought a OCZ RevoDrive3 and was
bitten by the lack of Linux support.

Notes from testing:
-------------------
- SMART works.
- VPD Device Identification is "OCZ-REVODRIVE3"
- Thin provisioning/TRIM seems to be implemented as WRITE SAME UNMAP,
  with deterministic (non-zero) read after TRIM, but I'm not sure if it
  works 100% in my testing.
- Some of the tuning in the firmware seems to ensure much better
  performance when in a RAID0 setup than using the two devices
  seperately.

I have not tested booting from the SSD, because all of this was
developed and tested remotely from the actual hardware.
Signed-off-by: NRobin H. Johnson <robbat2@gentoo.org>
Thanks-To: Gordon Pritchard <gordp@sfu.ca>
Acked-by: NXiangliang Yu <yuxiangl@marvell.com>
Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>

These will be shared between the sfc driver and a PCI quirk.
Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>

Adding to pci_id.h and the device table for ioat.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NDan Williams <dan.j.williams@intel.com>

And change iSCSI RQ doorbell size from 16B to 64B to match new firmware.
Signed-off-by: NMichael Chan <mchan@broadcom.com>
Signed-off-by: NEddie Wai <eddie.wai@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NManoj Iyer <manoj.iyer@canonical.com>
Cc: <stable@kernel.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Initialise model-specific DAC and ADC parts.
Add controls for output and mic source selection.
Rename some mixer controls according to ControlNames.txt.
Remove Playback switches for Line-in and IEC958-in - these
were controlling the input mute/unmute which affected
capture too.  Use the capture switches to control the
input mute/unmute instead - it's less confusing.
Initialise the WM8775 to invert the left-right clock
to swap the left and right channels of the mic and aux
input.
Signed-off-by: NHarry Butterworth <heb1001@gmail.com>
Signed-off-by: NTakashi Iwai <tiwai@suse.de>

Add I/O based support for serial and parallel ports of the following
chips:

Vendor: Moschip (0x9710)

Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)

On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.

Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.

The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.

[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdfSigned-off-by: NNicos Gollan <gtdev@spearhead.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

This adds the PCI ID for the xHCI (USB 3.0) host controller in the Intel
Panther Point chipset.  It will be used by both the EHCI and xHCI driver
in the following patches.
Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>