1. 02 2月, 2021 1 次提交
  2. 15 12月, 2020 1 次提交
  3. 26 11月, 2020 3 次提交
  4. 19 11月, 2020 1 次提交
  5. 12 11月, 2020 1 次提交
  6. 31 10月, 2020 1 次提交
  7. 05 10月, 2020 1 次提交
    • V
      net: dsa: propagate switchdev vlan_filtering prepare phase to drivers · 2e554a7a
      Vladimir Oltean 提交于
      A driver may refuse to enable VLAN filtering for any reason beyond what
      the DSA framework cares about, such as:
      - having tc-flower rules that rely on the switch being VLAN-aware
      - the particular switch does not support VLAN, even if the driver does
        (the DSA framework just checks for the presence of the .port_vlan_add
        and .port_vlan_del pointers)
      - simply not supporting this configuration to be toggled at runtime
      
      Currently, when a driver rejects a configuration it cannot support, it
      does this from the commit phase, which triggers various warnings in
      switchdev.
      
      So propagate the prepare phase to drivers, to give them the ability to
      refuse invalid configurations cleanly and avoid the warnings.
      
      Since we need to modify all function prototypes and check for the
      prepare phase from within the drivers, take that opportunity and move
      the existing driver restrictions within the prepare phase where that is
      possible and easy.
      
      Cc: Florian Fainelli <f.fainelli@gmail.com>
      Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
      Cc: Hauke Mehrtens <hauke@hauke-m.de>
      Cc: Woojung Huh <woojung.huh@microchip.com>
      Cc: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
      Cc: Sean Wang <sean.wang@mediatek.com>
      Cc: Landen Chao <Landen.Chao@mediatek.com>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Vivien Didelot <vivien.didelot@gmail.com>
      Cc: Jonathan McDowell <noodles@earth.li>
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Cc: Claudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2e554a7a
  8. 19 9月, 2020 4 次提交
  9. 02 9月, 2020 1 次提交
  10. 24 8月, 2020 1 次提交
  11. 25 7月, 2020 3 次提交
  12. 20 7月, 2020 1 次提交
    • R
      net: dsa: mv88e6xxx: fix in-band AN link establishment · fad58190
      Russell King 提交于
      If in-band negotiation or fixed-link modes are specified for a DSA
      port, the DSA code will force the link down during initialisation. For
      fixed-link mode, this is fine, as phylink will manage the link state.
      However, for in-band mode, phylink expects the PCS to detect link,
      which will not happen if the link is forced down.
      
      There is a related issue that in in-band mode, the link could come up
      while we are making configuration changes, so we should force the link
      down prior to reconfiguring the interface mode.
      
      This patch addresses both issues.
      
      Fixes: 3be98b2d ("net: dsa: Down cpu/dsa ports phylink will control")
      Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>
      Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      fad58190
  13. 13 7月, 2020 1 次提交
  14. 06 7月, 2020 1 次提交
  15. 11 5月, 2020 1 次提交
    • V
      net: dsa: permit cross-chip bridging between all trees in the system · f66a6a69
      Vladimir Oltean 提交于
      One way of utilizing DSA is by cascading switches which do not all have
      compatible taggers. Consider the following real-life topology:
      
            +---------------------------------------------------------------+
            | LS1028A                                                       |
            |               +------------------------------+                |
            |               |      DSA master for Felix    |                |
            |               |(internal ENETC port 2: eno2))|                |
            |  +------------+------------------------------+-------------+  |
            |  | Felix embedded L2 switch                                |  |
            |  |                                                         |  |
            |  | +--------------+   +--------------+   +--------------+  |  |
            |  | |DSA master for|   |DSA master for|   |DSA master for|  |  |
            |  | |  SJA1105 1   |   |  SJA1105 2   |   |  SJA1105 3   |  |  |
            |  | |(Felix port 1)|   |(Felix port 2)|   |(Felix port 3)|  |  |
            +--+-+--------------+---+--------------+---+--------------+--+--+
      
      +-----------------------+ +-----------------------+ +-----------------------+
      |   SJA1105 switch 1    | |   SJA1105 switch 2    | |   SJA1105 switch 3    |
      +-----+-----+-----+-----+ +-----+-----+-----+-----+ +-----+-----+-----+-----+
      |sw1p0|sw1p1|sw1p2|sw1p3| |sw2p0|sw2p1|sw2p2|sw2p3| |sw3p0|sw3p1|sw3p2|sw3p3|
      +-----+-----+-----+-----+ +-----+-----+-----+-----+ +-----+-----+-----+-----+
      
      The above can be described in the device tree as follows (obviously not
      complete):
      
      mscc_felix {
      	dsa,member = <0 0>;
      	ports {
      		port@4 {
      			ethernet = <&enetc_port2>;
      		};
      	};
      };
      
      sja1105_switch1 {
      	dsa,member = <1 1>;
      	ports {
      		port@4 {
      			ethernet = <&mscc_felix_port1>;
      		};
      	};
      };
      
      sja1105_switch2 {
      	dsa,member = <2 2>;
      	ports {
      		port@4 {
      			ethernet = <&mscc_felix_port2>;
      		};
      	};
      };
      
      sja1105_switch3 {
      	dsa,member = <3 3>;
      	ports {
      		port@4 {
      			ethernet = <&mscc_felix_port3>;
      		};
      	};
      };
      
      Basically we instantiate one DSA switch tree for every hardware switch
      in the system, but we still give them globally unique switch IDs (will
      come back to that later). Having 3 disjoint switch trees makes the
      tagger drivers "just work", because net devices are registered for the
      3 Felix DSA master ports, and they are also DSA slave ports to the ENETC
      port. So packets received on the ENETC port are stripped of their
      stacked DSA tags one by one.
      
      Currently, hardware bridging between ports on the same sja1105 chip is
      possible, but switching between sja1105 ports on different chips is
      handled by the software bridge. This is fine, but we can do better.
      
      In fact, the dsa_8021q tag used by sja1105 is compatible with cascading.
      In other words, a sja1105 switch can correctly parse and route a packet
      containing a dsa_8021q tag. So if we could enable hardware bridging on
      the Felix DSA master ports, cross-chip bridging could be completely
      offloaded.
      
      Such as system would be used as follows:
      
      ip link add dev br0 type bridge && ip link set dev br0 up
      for port in sw0p0 sw0p1 sw0p2 sw0p3 \
      	    sw1p0 sw1p1 sw1p2 sw1p3 \
      	    sw2p0 sw2p1 sw2p2 sw2p3; do
      	ip link set dev $port master br0
      done
      
      The above makes switching between ports on the same row be performed in
      hardware, and between ports on different rows in software. Now assume
      the Felix switch ports are called swp0, swp1, swp2. By running the
      following extra commands:
      
      ip link add dev br1 type bridge && ip link set dev br1 up
      for port in swp0 swp1 swp2; do
      	ip link set dev $port master br1
      done
      
      the CPU no longer sees packets which traverse sja1105 switch boundaries
      and can be forwarded directly by Felix. The br1 bridge would not be used
      for any sort of traffic termination.
      
      For this to work, we need to give drivers an opportunity to listen for
      bridging events on DSA trees other than their own, and pass that other
      tree index as argument. I have made the assumption, for the moment, that
      the other existing DSA notifiers don't need to be broadcast to other
      trees. That assumption might turn out to be incorrect. But in the
      meantime, introduce a dsa_broadcast function, similar in purpose to
      dsa_port_notify, which is used only by the bridging notifiers.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Reviewed-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NJakub Kicinski <kuba@kernel.org>
      f66a6a69
  16. 30 4月, 2020 1 次提交
    • J
      net: dsa: mv88e6xxx: remove duplicate assignment of struct members · 98123074
      Jason Yan 提交于
      These struct members named 'phylink_validate' was assigned twice:
      
      static const struct mv88e6xxx_ops mv88e6190_ops = {
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      };
      
      static const struct mv88e6xxx_ops mv88e6190x_ops = {
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      	......
      	.phylink_validate = mv88e6390x_phylink_validate,
      };
      
      static const struct mv88e6xxx_ops mv88e6191_ops = {
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      };
      
      static const struct mv88e6xxx_ops mv88e6290_ops = {
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      	......
      	.phylink_validate = mv88e6390_phylink_validate,
      };
      
      Remove all the first one and leave the second one which are been used in
      fact. Be aware that for 'mv88e6190x_ops' the assignment functions is
      different while the others are all the same. This fixes the following
      coccicheck warning:
      
      drivers/net/dsa/mv88e6xxx/chip.c:3911:48-49: phylink_validate: first
      occurrence line 3965, second occurrence line 3967
      drivers/net/dsa/mv88e6xxx/chip.c:3970:49-50: phylink_validate: first
      occurrence line 4024, second occurrence line 4026
      drivers/net/dsa/mv88e6xxx/chip.c:4029:48-49: phylink_validate: first
      occurrence line 4082, second occurrence line 4085
      drivers/net/dsa/mv88e6xxx/chip.c:4184:48-49: phylink_validate: first
      occurrence line 4238, second occurrence line 4242
      
      Fixes: 4262c38d ("net: dsa: mv88e6xxx: Add SERDES stats counters to all 6390 family members")
      Signed-off-by: NJason Yan <yanaijie@huawei.com>
      Reviewed-by: NRussell King <rmk+kernel@armlinux.org.uk>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      98123074
  17. 15 4月, 2020 1 次提交
  18. 16 3月, 2020 5 次提交
  19. 12 3月, 2020 1 次提交
  20. 28 2月, 2020 2 次提交
  21. 27 2月, 2020 1 次提交
  22. 17 2月, 2020 3 次提交
  23. 20 1月, 2020 1 次提交
  24. 09 1月, 2020 1 次提交
    • F
      net: dsa: Get information about stacked DSA protocol · 4d776482
      Florian Fainelli 提交于
      It is possible to stack multiple DSA switches in a way that they are not
      part of the tree (disjoint) but the DSA master of a switch is a DSA
      slave of another. When that happens switch drivers may have to know this
      is the case so as to determine whether their tagging protocol has a
      remove chance of working.
      
      This is useful for specific switch drivers such as b53 where devices
      have been known to be stacked in the wild without the Broadcom tag
      protocol supporting that feature. This allows b53 to continue supporting
      those devices by forcing the disabling of Broadcom tags on the outermost
      switches if necessary.
      
      The get_tag_protocol() function is therefore updated to gain an
      additional enum dsa_tag_protocol argument which denotes the current
      tagging protocol used by the DSA master we are attached to, else
      DSA_TAG_PROTO_NONE for the top of the dsa_switch_tree.
      Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4d776482
  25. 07 1月, 2020 2 次提交