- 08 8月, 2019 2 次提交
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由 Marc Gonzalez 提交于
QCOM_A53PLL and QCOM_CLK_APCS_MSM8916 stand out as the only options built by default. Let's bring them back in line with the rest. Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr> Link: https://lkml.kernel.org/r/d654907d-a3a2-a00f-d6f5-3a34ae25ebcf@free.frReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Acked-by: NGeorgi Djakov <georgi.djakov@linaro.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Deepak Katragadda 提交于
Add the clocks supported in global clock controller which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: NDeepak Katragadda <dkatraga@codeaurora.org> Signed-off-by: NTaniya Das <tdas@codeaurora.org> [vkoul: port to upstream and tidy-up port to new parent scheme Add comments for critical clocks]] Signed-off-by: NVinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20190722074348.29582-6-vkoul@kernel.orgSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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- 21 5月, 2019 1 次提交
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由 Thomas Gleixner 提交于
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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- 12 4月, 2019 1 次提交
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由 Bjorn Andersson 提交于
The Turing Clock Controller provides resources related to running the Turing subsystem. PM runtime is used to ensure that the associated AHB clock is ticking while the clock framework is accessing the registers in the Turing clock controller. Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 12 1月, 2019 1 次提交
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由 Marc Gonzalez 提交于
If QCOM_GDSC is disabled, gdsc_register() returns -ENOSYS, which causes gcc_msm8998_probe() to fail. Select QCOM_GDSC to solve the problem. gcc-msm8998: probe of 100000.clock-controller failed with error -38 Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr> Fixes: b5f5f525 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 11 12月, 2018 1 次提交
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由 Stephen Boyd 提交于
We duplicate the 'depends on' in almost every Kconfig here, and it's getting out of hand now that we have tens of options for various SoC drivers here. Let's clean it up a little by making a menuconfig for a submenu and adding an if wrapper around the driver section. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 04 12月, 2018 1 次提交
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由 Taniya Das 提交于
Add support for the lpass clock controller found on SDM845 based devices. This would allow lpass peripheral loader drivers to control the clocks to bring the subsystem out of reset. LPASS clocks present on the global clock controller would be registered with the clock framework based on the protected-clock flag. Also do not gate these clocks if they are left unused, as the lpass clocks require the global clock controller lpass clocks to be enabled before they are accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock access. Signed-off-by: NTaniya Das <tdas@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 28 11月, 2018 1 次提交
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由 Amit Nischal 提交于
Add support for the graphics clock controller found on SDM845 based devices. This would allow graphics drivers to probe and control their clocks. Signed-off-by: NAmit Nischal <anischal@codeaurora.org> Signed-off-by: NTaniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Collapse return in probe into less lines] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 18 10月, 2018 4 次提交
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由 Stephen Boyd 提交于
The Krait CPU clocks are made up of a primary mux and secondary mux for each CPU and the L2, controlled via cp15 accessors. For Kraits within KPSSv1 each secondary mux accepts a different aux source, but on KPSSv2 each secondary mux accepts the same aux source. Cc: <devicetree@vger.kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NSricharan R <sricharan@codeaurora.org> Tested-by: NCraig Tatlor <ctatlor97@gmail.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Stephen Boyd 提交于
The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Cc: <devicetree@vger.kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NSricharan R <sricharan@codeaurora.org> Tested-by: NCraig Tatlor <ctatlor97@gmail.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Stephen Boyd 提交于
The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15 registers. Support these clocks. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NSricharan R <sricharan@codeaurora.org> Tested-by: NCraig Tatlor <ctatlor97@gmail.com> [sboyd@kernel.org: Move hidden config to top outside of the visible qcom config zone so that menuconfig looks nice] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Stephen Boyd 提交于
On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Cc: <devicetree@vger.kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NSricharan R <sricharan@codeaurora.org> Tested-by: NCraig Tatlor <ctatlor97@gmail.com> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 17 10月, 2018 2 次提交
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由 Shefali Jain 提交于
Add the clocks supported in global clock controller which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: NShefali Jain <shefjain@codeaurora.org> Signed-off-by: NTaniya Das <tdas@codeaurora.org> Co-developed-by: NTaniya Das <tdas@codeaurora.org> Signed-off-by: NAnu Ramanathan <anur@codeaurora.org> [bamse, vkoul: rebase and tidyup for upstream] Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NVinod Koul <vkoul@kernel.org> Acked-by: NRob Herring <robh@kernel.org> [sboyd@kernel.org: Lowercase hex] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Taniya Das 提交于
Add support for the global clock controller found on SDM660 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. Signed-off-by: NTaniya Das <tdas@codeaurora.org> [craig: rename parents to fit upstream, and other cleanups] Signed-off-by: NCraig Tatlor <ctatlor97@gmail.com> Acked-by: NRob Herring <robh@kernel.org> [sboyd@kernel.org: Rename gcc_660 to gcc_sdm660 and fix numbering of defines to avoid duplicates] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 31 8月, 2018 1 次提交
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由 Amit Nischal 提交于
Add support for the camera clock controller found on SDM845 based devices. This would allow camera drivers to probe and control their clocks. Signed-off-by: NAmit Nischal <anischal@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 01 8月, 2018 1 次提交
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由 Taniya Das 提交于
Add support for the display clock controller found on SDM845 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: NTaniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 17 7月, 2018 1 次提交
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由 Taniya Das 提交于
Add the RPMh clock driver to control the RPMh managed clock resources on some of the Qualcomm Technologies, Inc. SoCs. Signed-off-by: NTaniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Clean up whitespace, indentation, remove cmd_db_ready check] Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 02 6月, 2018 1 次提交
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由 Amit Nischal 提交于
Add support for the video clock controller found on SDM845 based devices. This would allow video drivers to probe and control their clocks. Signed-off-by: NAmit Nischal <anischal@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 09 5月, 2018 1 次提交
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由 Taniya Das 提交于
Add support for the global clock controller found on SDM845 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: NTaniya Das <tdas@codeaurora.org> Signed-off-by: NAmit Nischal <anischal@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 17 4月, 2018 1 次提交
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由 Joonwoo Park 提交于
Add support for the global clock controller found on MSM8998 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: NJoonwoo Park <joonwoop@codeaurora.org> Signed-off-by: NImran Khan <kimran@codeaurora.org> Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> [bjorn: Specify regs for alpha_plls, fix white spaces and add binding] Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 03 1月, 2018 2 次提交
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由 Georgi Djakov 提交于
Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org> Tested-by: NAmit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Include rcg header for parent_map, drop multiple unneeded includes, add COMPILE_TEST to APCS depends, made tristate/modular] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Georgi Djakov 提交于
The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org> Tested-by: NAmit Kucheria <amit.kucheria@linaro.org> [sboyd@codeaurora.org: Move to devm provider registration, NUL terminate frequency table, made tristate/modular] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 07 12月, 2017 1 次提交
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由 Tirupathi Reddy 提交于
Clkdiv module provides a clock output on the PMIC with CXO as the source. This clock can be routed through PMIC GPIOs. Add a device driver to configure this clkdiv module. Signed-off-by: NTirupathi Reddy <tirupath@codeaurora.org> [sboyd: Simplified code and moved to devm clk provider APIs] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 20 6月, 2017 1 次提交
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由 Abhishek Sahu 提交于
This patch adds support for the global clock controller found on the ipq8074 based devices. This includes UART, I2C, SPI etc. Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org> Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 11 11月, 2016 3 次提交
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由 Georgi Djakov 提交于
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Georgi Djakov 提交于
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.cSigned-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> Acked-by: NRob Herring <robh@kernel.org> [sboyd@codeaurora.org: Remove useless braces for single line if] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Bastian Köcher 提交于
The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by: NBastian Köcher <mail@kchr.de> [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com> [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 26 8月, 2016 1 次提交
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由 Srinivas Kandagatla 提交于
This patch selects QCOM_GDSC Kconfig for msm8996 GCC and MMCC clock controllers, as these provide some of the gdscs on the SOC. Also selecting this config will make it align with other drivers which do the same. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Fixes: 52111672 ("clk: qcom: gdsc: Add GDSCs in msm8996 GCC") Fixes: 7e824d50 ("clk: qcom: gdsc: Add mmcc gdscs for msm8996 family") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 16 8月, 2016 1 次提交
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由 Neil Armstrong 提交于
In order to support the Qualcomm MDM9615 SoC, add support for the Global and LPASS Clock Controllers. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 26 2月, 2016 1 次提交
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由 Varadarajan Narayanan 提交于
This patch adds support for the global clock controller found on the IPQ4019 based devices. This includes UART, I2C, SPI etc. Signed-off-by: NPradeep Banavathi <pradeepb@codeaurora.org> Signed-off-by: NSenthilkumar N L <snlakshm@codeaurora.org> Signed-off-by: NVaradarajan Narayanan <varada@codeaurora.org> Signed-off-by: NMatthew McClintock <mmcclint@codeaurora.org> Acked-by: NAndy Gross <andy.gross@linaro.org> [sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 01 12月, 2015 2 次提交
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由 Stephen Boyd 提交于
Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 09 10月, 2015 1 次提交
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由 Stephen Boyd 提交于
Having this hidden config below the COMMON_CLK_QCOM config causes menuconfig to stop indenting config items after it. <*> Support for Qualcomm's clock controllers {M} APQ8084 Global Clock Controller <M> APQ8084 Multimedia Clock Controller {M} IPQ806x Global Clock Controller <M> IPQ806x LPASS Clock Controller <M> MSM8660 Global Clock Controller <M> MSM8916 Global Clock Controller {M} APQ8064/MSM8960 Global Clock Controller <M> APQ8064/MSM8960 LPASS Clock Controller <M> MSM8960 Multimedia Clock Controller {M} MSM8974 Global Clock Controller <M> MSM8974 Multimedia Clock Controller Move it up above anything else so that we don't get odd indenting. Cc: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 17 9月, 2015 6 次提交
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由 Stephane Viau 提交于
Add the GDSC instances that exist as part of apq8084 MMCC block. Signed-off-by: NStephane Viau <sviau@codeaurora.org> Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Rajendra Nayak 提交于
Add the GDSC instances that exist as part of apq8084 GCC block Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Add the GDSC instances that exist as part of msm8974 MMCC block Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
There's just one GDSC as part of the msm8974 GCC block. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Rajendra Nayak 提交于
Add all data for the GDSCs which are part of msm8916 GCC block. Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
GDSCs (Global Distributed Switch Controllers) are responsible for safely collapsing and restoring power to peripherals in the SoC. These are best modelled as power domains using genpd and given the registers are scattered throughout the clock controller register space, its best to have the support added through the clock driver. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 08 4月, 2015 1 次提交
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Support for Qualcomm's clock controllers should be available only on Qualcomm platforms. Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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